CS61304A Cirrus Logic, Inc., CS61304A Datasheet - Page 23

• Manufacturer Part Number: CS61304A
• Description: T1-E1 Line Interface Unit for CPE-ISDN PRI
• Manufacturer: Cirrus Logic, Inc.

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
MODE - Mode Select, Pin 5.
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
SCLK - Serial Clock, Pin 27. (Host Mode)
SDI - Serial Data Input, Pin 24. (Host Mode)
SDO - Serial Data Output, Pin 25. (Host Mode)
DS156PP2
Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. Also controls the receiver
slicing level and the line code in Extended Hardware Mode.
Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the
receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless
overridden by a TAOS request. Inputs on RTIP and RRING are ignored.
Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin puts the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 V selects the Extended Hardware
Mode, where configuration and status are controlled by discrete pins. When floating MODE,
there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2).
Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2,
RLOOP, LLOOP and TAOS inputs.
Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).
Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator (if active) and through the driver back to the line. The recovered signal is also sent to
RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.
Data for the on-chip register. Sampled on the rising edge of SCLK.
Status and control information from the on-chip register. If CLKE is high SDO is valid on the
rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to or after bit D7 is output.
CS61304A
23