FMS6501 Fairchild Semiconductor, FMS6501 Datasheet - Page 9

• Manufacturer Part Number: FMS6501
• Description: 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
• Manufacturer: Fairchild Semiconductor

© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
Acknowledge
The data bytes transferred between the START and
STOP conditions from transmitter to receiver is unlim-
ited. Each byte of eight bits is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on the bus by the transmitter, during which the master
generates an extra acknowledge-related clock pulse. A
slave receiver must generate an acknowledge after the
reception of each byte. A master receiver must generate
an acknowledge after the reception of each byte that has
been clocked out of the slave transmitter.
I
Before any data is transmitted on the I
that should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
2
C Bus Protocol
Figure 7. Write a Register Address to the Pointer Register, Then Write Data to the Selected Register
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
START BY
MASTER
SCL
SDA
START
condition
A6
1
A5
SERIAL BUS ADDRESS BYTE
A4
Figure 6. Acknowledgement on the I
FRAME1
2
A3
C bus, the device
1
SDA (CONTINUED)
SCL (CONTINUED)
A2
A1
A0
R/W
ACK. BY
FMS6501
2
9
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse so the SDA line
is stable LOW during the HIGH period of the acknowl-
edge-related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte clocked out of the slave. In
this event, the transmitter must leave the data line HIGH
to enable the master to generate a STOP condition.
start procedure. The I
write to the FMS6501 is shown in Figure 5.
D7
1
9
D7
D6
1
D6
D5
2
ADDRESS POINTER REGISTER BYTE
D5
D4
C Bus
DATA BYTE
D4
FRAME 3
D3
8
FRAME 2
D3
D2
2
C bus configuration for a data
D2
D1
D1
D0
clock pulse for
acknowledgement
ACK. BY
FMS6501
D0
9
9
ACK. BY
FMS6501
9
STOP BY
MASTER
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