MT9HTF12872CHY-667 Micron Semiconductor Products, MT9HTF12872CHY-667 Datasheet - Page 9

• Manufacturer Part Number: MT9HTF12872CHY-667
• Description: 512mb, 1gb X72, Ecc, Sr 200-pin Ddr2 Sdram Socdimm
• Manufacturer: Micron Semiconductor Products

Table 10:
PDF: 09005aef828eddb4/Source: 09005aef828edcf5
HTF9C64_128x72CH.fm - Rev. B 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
between valid commands; Address bus inputs are switching; Data
pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
t
inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All device banks open; Continuous
burst reads; I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
t
Other control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks
interleaving reads; I
t
Address bus inputs are stable during deselects; Data bus inputs are
switching
1 ×
RC =
RAS =
CK =
CK =
RAS =
RAS =
RAS =
RFC (I
RCD =
t
CK (I
t
t
t
DD
RC (I
CK (I
CK (I
t
t
t
t
t
RAS MIN (I
RAS MAX (I
RAS MAX (I
RAS MAX (I
RCD (I
) interval; CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
DD
);
OUT
),
DDR2 I
Values are shown for the MT9HTF12872 DDR2 SDRAM only and are computed from the values specified in
the 1Gb (128 Meg x 8) component data sheet
); CKE is HIGH, S# is HIGH; Other control and address bus
); CKE is LOW; Other control and address
t
DD
CK =
t
RAS =
DD
); CKE is HIGH, S# is HIGH between valid commands;
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
DD
DD
DD
DD
OUT
t
CK (I
),
4W
),
),
),
DD
t
t
RAS MIN (I
RCD =
t
t
t
= 0mA; BL = 4, CL = CL (I
RP =
RP =
RP =
t
CK =
DD
Specifications and Conditions – 1GB
),
t
CK =
t
t
t
DD
t
RP (I
RP (I
RP (I
t
t
RC =
RCD (I
CK (I
), AL = 0;
DD
t
DD
DD
DD
CK (I
t
DD
RC (I
); CKE is HIGH, S# is HIGH between
DD
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
); REFRESH command at every
); CKE is HIGH, S# is HIGH
DD
512MB, 1GB (x72, ECC, SR) 200-Pin DDR2 SDRAM SOCDIMM
DD
DD
t
),
CK =
),
), AL = 0;
t
RC =
t
RRD =
t
CK (I
DD
t
t
RC (I
CK =
), AL =
t
CK =
t
t
DD
CK =
RRD (I
t
CK =
DD
),
t
CK (I
t
t
),
t
OUT
CK (I
CK =
t
RCD (I
CK (I
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[2] = 1
DD
CK (I
9
DD
),
= 0mA;
DD
t
),
DD
CK (I
DD
DD
),
); CKE
),
) -
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
);
Symbol
I
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
3Pf
3Ps
4W
2Q
2N
3N
2P
4R
0
1
5
6
7
1,440
1,440
2,115
3,015
-80E/
-800
810
990
450
450
360
540
63
90
63
©2007 Micron Technology, Inc. All rights reserved.
1,215
1,215
1,935
2,520
-667
765
900
360
360
270
495
I
63
90
63
DD
Specifications
1,125
1,125
1,890
2,430
-53E
630
855
360
270
270
405
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA