SMM766B SUMMIT Microelectronics, Inc:, SMM766B Datasheet
SMM766B
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SMM766B Summary of contents
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... Internal REFERENCE Figure 1 – Applications schematic using the SMM766B controller to actively control the output levels DC/DC converters while also providing power-on/off, cascade sequencing and output margining. Note: This is an applications example only. Some pins, components and values are not shown. ...
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... Ordering Information…..……………………….… ……37 Terminology And Definitions……………………… …..38 Legal Notice………………………………………… …..39 2122 3.0 5/5/2008 SMM766B 2 ...
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... Figure 2 – Example power supply sequencing and system start-up initialization using the SMM766B. Cascade sequencing ensures that all supplies in the previous sequence position are valid before the next channel is released. Using the SMM766B any order of supply sequencing can be applied. GENERAL DESCRIPTION The SMM766B is a highly integrated and accurate power supply controller, monitor, and sequencer ...
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... VM F CAP F TRIM A TRIM_CAP A Active DC Output Control (ADOC TM ) TRIM F TRIM_CAP F VREF FILT_CAP Figure 3 – SMM766B Internal Functional Block Diagram. Summit Microelectronics, Inc VDD_CAP 3.6V or Power 5.5V Supply Regulator Arbitrator UVLO Control Temperature Sensor Memory, Limit and Status Registers 2122 3.0 5/5/2008 SMM766B PWR_ON FS# ...
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... PWR_ON the part will sequence the supplies on, during the falling edge the part will sequence the supplies off. This pin must be tied high through an external pull-up resistor. Note: The SMM766B does not monitor for faults during power-on/off sequencing. FS# (Force Shutdown open drain active low bi-directional pin. FS# is used to immediately turn off all converter enable signals (PUP outputs) when a fault is detected ...
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... SEQ_LINK (Sequence-Link™ open drain bi-directional pin. This pin should be attached to other Sequence-Link devices, during linked operation. SEQ_LINK must be pulled high through an external pull-up resistor when multiple Sequence-Link devices are used. When the SMM766B is not used with another Sequence-Link device, SEQ_LINK should be tied directly to ground. ...
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... PACKAGE AND PIN CONFIGURATION SDA SCL A2 MR# PWR_ON FS# FAULT# HEALTHY RST# AIN1 AIN2 GND Summit Microelectronics, Inc 48 LEAD TQFP 2122 3.0 5/5/2008 SMM766B 36 VMB 35 TRIM_CAPC 34 TRIMC 33 PUPC 32 CAPC 31 VMC 30 TRIM_CAPD 29 TRIMD 28 PUPD 27 CAPD 26 VMD 25 TRIM_CAPE 7 ...
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... VDD floating TRIM sourcing maximum current TRIM sinking maximum current Depends on TRIM range of DC-DC converter Max acceptable board and cap leakage is 50nA Internally regulated to 3.6V Internally regulated to 5.5V VM pin VM, AIN1/AIN2 pins 2122 3.0 5/5/2008 SMM766B (Commercial) ...............0°C to +70°C B ............................ 6.0V to 14. Min Typ Max 2.7 5 ...
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... Total PUPx I SINK -0.50 ≥ = 6ma, V 3.5V, SENSE ° ° +50 C Internal V =1.25V, REF Total PUPx I = 6ma, -0.50 SINK ° ° +50 C 2122 3.0 5/5/2008 SMM766B Typ Max Unit VDD_CAP 0 VDD_CAP VDD_CAP 0 VDD_CAP 0.4 V 1.0 mA µA 1 ...
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... Minimum resolution for which no missing codes are guaranteed Conversion rate = 500Hz Total ADC Read Error (Note 11) VMA-VMF Notes Minimum resolution for which no missing codes are guaranteed Conversion rate = 500Hz Total ADC Read Error (Note 12) 2122 3.0 5/5/2008 SMM766B Min Typ Max Unit 1 V 2.6 V 2.5 V ...
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... Note 12 – ADC accuracy can be improved using the following formula: 1024 * Limit(V)_NEW/(4 * VREF_ADC) Where Limit(V)_NEW = LIMIT(V)*(0.99965 +0.00035*LIMIT(V)) - 0.011. VREF_ADC is the actual device voltage reference to 4 significant digits. Summit Microelectronics, Inc 2122 3.0 5/5/2008 SMM766B from all PUPx pins should SINK 11 ...
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... A – F Update time for ADOC per channel Slow Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1µF Fast Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1µF Auto-Monitor suspended indefinitely faulty I C transaction 2122 3.0 5/5/2008 SMM766B Min Typ Max Unit -25 t +25 % DPON -25 t +25 ...
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... Note 13 Note 13 250 0 Noise suppression Configuration registers Memory array HIGH LOW HD:DAT SU:DAT HD:STA Figure 4 - Basic I C Serial Interface Timing 2122 3.0 5/5/2008 SMM766B 100kHz 400kHz Typ Max Min Typ Max 100 0 400 1.3 0.6 1.3 0.6 0.6 0.6 3.5 0.2 0.9 0.2 1000 1000 300 300 150 ...
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... TIMING DIAGRAMS (CONTINUED) Sequence Position PUP t A DPONA VM A PUP PUP PUP Figure 5 - The SMM766B cascade sequencing the supplies on and then monitoring for fault conditions. Sequence Position PUP PUP PUP t C DPOFFC VM C PUP t D DPOFFD ...
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... APPLICATIONS INFORMATION DEVICE OPERATION POWER SUPPLY The SMM766B can be powered by either a 12V input through the 12VIN pin 3.3V or 5.0V input through the VDD pin. The 12VIN pin feeds an internal programmable regulator that internally generates either 5.5V or 3.6V. A voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the VDD input ...
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... A forced shutdown will also be issued by the SMM766B when the next PWR_ON assertion occurs if the sequence termination timer is enabled. Following the forced shutdown, the SMM766B will latch off programmed for zero retries. If not programmed for zero retries, a power-on sequence will be initiated after 2 ...
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... PWR_ON pin, differently than those caused by a Fault-Triggered conditions, those caused by UV/OV violations or a sequence termination timer expiration. The mode in which either a Forced Shutdown or a power-off occurs effects how or whether the SMM766B will restart, and over-temperature the number of allowable retries permitted. 2122 3.0 5/5/2008 SMM766B ...
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... The SMM766B will then wait until all VM channels assigned to that sequence position are below the programmed OFF thresholds. At this point, the SMM766B will move to the next sequence position and begin to timeout the power-off delay times for the associated channels. This process continues until all of the channels in the sequence have turned off and are below their OFF thresholds ...
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... The second condition occurs when a user programmable operation or a power-off sequence thus resulting in a fault-triggered restart. In either case, the SMM766B will wait until all voltages have fallen below their user programmable OFF thresholds, after all channels are off, the PWR_ON pin outputs ...
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... This condition will continue 2 until “power-off clear” command is issued. PROGRAMABLE RETRIES In the event of a persistent system fault, the SMM766B may be programmed to limit the number of Fault-Triggered restarts it programmable setting ensures that the SMM766B will Summit Microelectronics, Inc not enter a hiccup-mode of operation, while still reducing susceptibility to transient fault conditions ...
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... Stop. Summit Microelectronics, Inc mode. The auto-monitor function is paused during transaction. This function is re-enabled by several methods as described in the diagrams below Transaction Addressing the SMM766B SA3 SA2 SA1 SA0 BA2 2 C Read Transaction Stop ...
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... C command write transaction, auto-monitor is re-enabled on the falling 2 C command write is any write to slave address 2 C Writes to Configuration, General Purpose Memory and Margin Control Registers Stop WD1 WD0 ACK 2 C write to configuration, general purpose memory or margin control registers, 2122 3.0 5/5/2008 SMM766B ~15ms 22 ...
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... AUTO-MONITOR Figure 9E: Auto-monitor is re-enabled on the falling edge of the internal system clock after the auto- monitor timer has timed out. The auto-monitor timer is enabled when auto-monitor is paused and is restarted on the falling edge of SCL. Summit Microelectronics, Inc ACK >25ms 2122 3.0 5/5/2008 SMM766B 23 ...
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... SYSTEM CLOCK (T=5us) AUTO-MONITOR Figure 9G: During the 250us A-to-D conversion time, the activity on SDA and SCL are ignored. Summit Microelectronics, Inc SA2 SA1 SA0 BA2 During A-to-D Conversion ACK WA ACK 2122 3.0 5/5/2008 SMM766B BA1 BA0 R/W NACK Start SA + R/W NACK x 8 ~250us 24 ...
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... Figure 9H: Auto-monitor is re-enabled on the falling edge of the internal system clock after the falling edge of SCL during the NACK following a invalid slave address after the conversion has completed. Summit Microelectronics, Inc 2 During A-to-D Conversion Start SA + R/W NACK (Invalid SA 2122 3.0 5/5/2008 SMM766B Start SA + R/W NACK (Invalid SA ...
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... Figure 10 - Timing Sequence recovering from a VDD_CAP Power ‘Brown-Out’ Summit Microelectronics, Inc off sequences. If the VDD_CAP voltage falls below 2.5V (Figure 10), an internal undervoltage lockout (UVLO) circuit will reset all internal logic. Once power has recovered above 2.6V the SMM766B will restart Command-Triggered power-off had been issued. 2.6V 2122 3.0 5/5/2008 ...
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... APPLICATIONS INFORMATION (CONTINUED) Figure 11 – SMM766B Distributed power applications schematic. The accuracy of the external reference (U10) sets the accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% Summit Microelectronics, Inc 2122 3.0 5/5/2008 SMM766B 27 ...
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... MR SDA 2 1 SCL 2 C serial bus connections to program the SMM766B. Note that the MR# 2122 3.0 5/5/2008 SMM766B 2 C serial bus format so that it can be directly An example of the connection This will ensure proper device Pin 10, Reserved Pin 9, 5V Pin 8, Reserved Pin 7, 10V ...
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... The bus address bits BA[1:0] are programmed into the configuration registers. Bus address bit BA[2] can be programmed as either 0 or biased by the A2 pin. The bus address accessed in the address byte of the serial data stream must match the setting in the SMM766B and on the A2 pin. Summit Microelectronics, Inc Any access to the SMM766B on the I temporarily halt the monitoring function ...
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... I C PROGRAMMING INFORMATION (CONTINUED) WRITE PROTECTION The SMM766B powers up into a write protected mode. Writing a code to the volatile write protection register can disable the write protection. The write protection register is located at address 87 1001 . BIN Writing 0101 to bits [7:4] of the write protection BIN register allow writes to the general-purpose memory ...
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... Data Data (16 SMM766B ...
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... 2122 3.0 5/5/2008 SMM766B Bus Address Data ( ...
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... Bus Address Data ( SMM766B ...
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... start ACK polling here Figure 24 – ADC Conversion Read 2 C “STOP” command after the write phase of the ADC conversion-read (as 2122 3.0 5/5/2008 SMM766B Data ...
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... RC1 The default device ordering number is SMM766BFC-752 programmed with the register contents as shown above and tested over the commercial temperature range with a VREF setting of 1.25V. Other standard external VREF voltage settings that can be specified and tested are values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300. ...
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... BSC 0.276 (7.00) Pin 1 Indicator A Summit Microelectronics, Inc 48 PIN TQFP PACKAGE (A) BSC (B) (B) (A) Ref Jedec M S-026 0.037 - 0.041 0.95 - 1.05 0.047 (1.2) B 2086 2.2 5/1/06 SMM766B Preliminary Information Inches (Millim eters) 0.02 (0.5) 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" MAX. 0.002 - 0.006 (0.05-0.15) DETAIL "B" BSC 0.039 Ref (1.00 Min to ...
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... PART MARKING SUMMIT SMM766BF Annn Pin 1 Drawing not to scale ORDERING INFORMATION SMM766B F Summit Part Number Package F=48 Lead TQFP Summit Microelectronics, Inc Summit Part Number Status Tracking Code xx (Blank, MS, ES, 01, 02,...) (Summit Use) AYYWW L Part Number suffix (Contains Customer specific ordering requirements) ...
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... ADC Analog to Digital Converter. Converts analog voltage to digital voltage. SMM766B represents all measured voltages by 10-bit digital reading. Retries The number of times the SMM766B will restart after a Fault-Triggered power-off or force- shutdown. Restart When the SMM766B begins power on sequencing, includes initial power-on sequence. ...
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... SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2007 SUMMIT MICROELECTRONICS, Inc. are registered trademarks of Summit Microelectronics Inc trademark of Philips Corporation ADOC and Sequence-Link Summit Microelectronics, Inc NOTICE PROGRAMMABLE POWER FOR A GREEN PLANET™ 2122 3.0 5/5/2008 SMM766B 39 ...