HM-6551FWDSLASH883 Intersil Corporation, HM-6551FWDSLASH883 Datasheet
HM-6551FWDSLASH883
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HM-6551FWDSLASH883 Summary of contents
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... Data Sheet 256 x 4 CMOS RAM The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems ...
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... Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge All lines positive logic-active high. 4. Three-State Buffers: A high → output active. 5. Data Latches: L High → and Q latches on falling edge HM-6551/883 HM-6551/883 A 5 GATED ROW ...
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... NOTE: 1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA TABLE 1. HM-6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL Output Low Voltage ...
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... TABLE 2. HM-6551/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL Chip Enable (1) TELQV Access Time Address Access (2) TAVQV Time Chip Select 1 (3) TS1LQX Output Enable Time Write Enable (4) TWLQZ Output Disable Time Chip Select 1 (5) TS1HQZ Output Disable Time ...
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... TABLE 3. HM-6551B/883 AND HM-6551/883 ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL Input Capacitance CI VCC = Open 1MHz, All Measurements Referenced to Device Ground Output Capacitance CO VCC = Open 1MHz, All Measurements Referenced to Device Ground NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes ...
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... The HM-6551/883 Read Cycle is initiated by the falling edge of E. This signal latches the input address word and S2 into on-chip registers providing the minimum setup and hold times are met. After the required hold time, these inputs may change state without affecting device operation. S2 acts as a high order address and simplifies decoding ...
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... Data may be modified an indefinite number of times during any write cycle (TELEH). The HM-6551/883 may be used on a common I/O bus structure by tying the input and output pins together. The multiplexing is accomplished internally by the W line. In the write cycle, when W goes low, the output buffers are forced to a high impedance state ...
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... F3 F3 NOTES: All resistors 47kΩ ±5 100kHz ±10 ÷ ÷ ÷ F12 = F11 ÷ 2. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V 0.01µF Min. 8 HM-6551/883 HM-6551/883 + IOH 1.5V - EQUIVALENT CIRCUIT HM-6551/883 CERDIP VCC C1 VCC ...
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... Type: SiO 2 ±1k Å Å Thickness: 8k Metallization Mask Layout W A4 VCC NOTE: Pin numbers correspond to DIP Package only. 9 HM-6551/883 HM-6551/883 WORST CASE CURRENT DENSITY: 1.337 x 10 LEAD TEMPERATURE (10s soldering): o ≤300 C HM-6551/883 A/ GND ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 HM-6551/883 F22.4 c1 LEAD FINISH ...