HT46RU25 Holtek Semiconductor Inc., HT46RU25 Datasheet
HT46RU25
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HT46RU25 Summary of contents
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... Real Time Clock (RTC) with 8-bit prescaler HALT function and wake-up feature reduce power consumption General Description The HT46RU25/HT46CU25 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to an- alog signals, such as those from sensors. The mask ver- sion HT46CU25 is fully pin and functionally compatible with the OTP version HT46RU25 device ...
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... Block Diagram Rev. 1.30 HT46RU25/HT46CU25 2 March 9, 2007 ...
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... Pin Assignment Rev. 1.30 HT46RU25/HT46CU25 3 March 9, 2007 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.30 HT46RU25/HT46CU25 Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by option (bit option). Software instructions determine the CMOS out- put or Schmitt trigger input with or without pull-high resistor (determine by pull-high options: bit option) ...
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... I/O Port Source Current OH R Pull-high Resistance PH V A/D Input Voltage AD Additional Power Consumption I ADC if A/D Converter is Used DNL ADC Differential Non-Linear INL ADC Integral Non-Linear Rev. 1.30 HT46RU25/HT46CU25 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V No load, f =4MHz, SYS ADC Off, UART Off ...
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... Low Voltage Width to Reset LVR t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Bus Clock Period IIC Note: *t =1/f SYS SYS Rev. 1.30 HT46RU25/HT46CU25 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 2.2V~5.5V 0 3.3V~5. Power-up or Wake-up from HALT 0.25 1 ...
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... S13 S12 S11 S10 S9 Note: *13~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.30 HT46RU25/HT46CU25 Program Counter - PC The program counter (PC bits wide and it controls the sequence in which the instructions stored in the pro- gram ROM are executed. The contents of the PC can specify a maximum of 16384 16 addresses. After ac- cessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1 ...
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... Note: *13~*0: Table location bits @7~@0: Table pointer bits Rev. 1.30 HT46RU25/HT46CU25 bank has 8192 16 bit and is selected by setting the bank pointer (BP.5; Bank0, BP=000XXXXXB; Bank1: BP=001XXXXXB). The JMP and CALL instructions pro- vide only 13 bits of address to allow branching within any 8K program memory. When doing a JMP or CALL instruction, the user must ensure that the bank pointer bit (BP ...
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... Precautions should be taken to avoid such cases which might cause unpredictable program branching. Rev. 1.30 HT46RU25/HT46CU25 Data Memory - RAM The data memory (RAM) has a structure of 628´8 bits, and is divided into two functional groups, namely; spe- cial function registers (52´ ...
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... RAM Mapping Rev. 1.30 HT46RU25/HT46CU25 Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH bits wide and contains, a ...
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... RXIF or TIDF or RIDF bit is set, a subroutine call to loca- tion 010H will occur. The related interrupt request flag (URIF) will be reset and the EMI bit cleared to disable further interrupts. Rev. 1.30 HT46RU25/HT46CU25 Function Status (0AH) Register 2 The I C Bus interrupt is initialized by setting the I interrupt request flag (HIF ...
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... Time base interrupt request flag (1=active; 0=inactive) 6 RTF Real time clock interrupt request flag (1=active; 0=inactive) Rev. 1.30 HT46RU25/HT46CU25 Once the interrupt request flags, composed of EIF, T0F, T1F, URIF, HIF and MFF, are set, they will remain in the 04H INTC0 and INTC1 registers until the interrupts are ser- 08H viced or cleared by a software instruction ...
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... For applications where precise RTC frequencies are essential, these components may be re- quired to provide frequency compensation due to different crystal manufacturing tolerances. Rev. 1.30 HT46RU25/HT46CU25 get a frequency reference, but two external capacitors between OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz). ...
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... QOSC 5~7 RTCC (09H) Register 12 /2 (option since s Time Base Real Time Clock 14 HT46RU25/HT46CU25 15 /f selected by options. If time Function multiplexer control inputs to select the real clock prescaler output Unused bit, read as 0 32768Hz OSC quick start-up oscillating ...
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... Examining the PDF and TO flags, the program can distinguish between different chip resets . Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Configuration (system clock Reset Timing Chart 15 HT46RU25/HT46CU25 Reset Circuit March 9, 2007 ...
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... In this operation mode, the timer/event counter begins counting not according to the logic level but to the tran- sient edges. In the case of counter overflows, the coun- ter is reloaded from the timer/event counter register and issues an interrupt request the other two modes, i.e., event and timer modes. 16 HT46RU25/HT46CU25 March 9, 2007 ...
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... HT46RU25/HT46CU25 WDT Time-out (HALT) (HALT)* 000H 000H xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 00u0 00uu uuuu uuuu uuuu uuuu ...
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... BRG xxxx xxxx xxxx xxxx Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.30 HT46RU25/HT46CU25 RES Reset RES Reset (Normal Operation) (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ...
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... The timer/event counter still contin- ues to operate until an overflow occurs. Rev. 1.30 HT46RU25/HT46CU25 Timer/Event Counter 2 PFD Source Option When the timer/event counter (reading TMR0/TMR1/ TMR2) is read, the clock is blocked to avoid errors, as this may results in a counting error ...
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... Defines the operating mode, T1M1, T1M0: 01=Event count mode (external clock) 6 T1M0 10=Timer mode (internal clock) 7 T1M1 11=Pulse width measurement mode 00=Unused Rev. 1.30 Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMR0C (0EH) Register Function TMR1C (11H) Register 20 HT46RU25/HT46CU25 March 9, 2007 ...
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... The input mode always remain in its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing the PA3 data register will enable the PFD output func- tion and writing 0 will force the PA3 to remain HT46RU25/HT46CU25 March 9, 2007 ...
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... Rev. 1.30 HT46RU25/HT46CU25 Input/Output Ports PC0/TX Input/Output Ports PC1/RX Input/Output Ports 22 March 9, 2007 ...
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... The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency f /64 for (6+2) bits mode SYS f /128 for (7+1) bits mode SYS 23 HT46RU25/HT46CU25 . The PWM regis- SYS AC (0~3) Duty Cycle DC+1 i< (0~1) Duty Cycle DC+1 i< ...
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... EOCB bit is cleared. The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the Rev. 1.30 HT46RU25/HT46CU25 (6+2) PWM Mode (7+1) PWM Mode A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select ...
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... PB7 PB7 PB7 PB7 PB7 AN7 Rev. 1.30 HT46RU25/HT46CU25 Function ACSR (27H) Register Function ADCR (26H) Register PB6 PB5 PB4 PB3 PB6 PB5 PB4 PB3 PB6 PB5 PB4 PB3 PB6 PB5 PB4 PB3 PB6 ...
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... Rev. 1.30 ACS0 Analog Input Channel Selection Bit5 Bit4 Bit3 ADRL (24H), ADRH (25H) Register /8 as the A/D clock SYS 26 HT46RU25/HT46CU25 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Bit2 Bit1 Bit0 March 9, 2007 ...
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... Since low voltage state has to be maintained in its original state for over 1ms, therefore after a 1ms delay, the device enters the reset mode. Rev. 1.30 HT46RU25/HT46CU25 A/D Conversion Timing The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock ...
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... Set HEN bit of the I (HCR) bit 0 to enable the I 3: Set EHI bit of the interrupt control register 1 2 (INTC1) bit 0 to enable the I C Bus, 28 HT46RU25/HT46CU25 C Bus, the slave device must read Bus receives Bus interrupt. In the ...
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... HAAS and HCF is set. HCF is cleared to 0 when one data byte is being transferred, HCF is set to 1 indicating 7 HCF 8-bit data communication has been finished. Rev. 1.30 HT46RU25/HT46CU25 Function 2 C Bus function HCR (21H) Register Function 2 C Bus is busy and HBB is cleared to 0 means that the I ...
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... I Rev. 1.30 C Communication Timing Diagram 30 HT46RU25/HT46CU25 March 9, 2007 ...
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... C Bus, so the slave device must read data 2 from the I C Bus as a receiver. Rev. 1.30 HT46RU25/HT46CU25 Acknowledge Bit One of the slave device generates an acknowledge signal, when the slave address is matched. The master device can check this acknowledge bit to know if the slave device accepts the calling address ...
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... UART Bus Serial Interface The HT46RU25/HT46CU25 devices contain an inte- grated full-duplex asynchronous serial communications UART interface that enables communication with exter- nal devices that contain a serial interface. The UART function has many features and can transmit and re- ceive data serially by transferring a frame of data with ...
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... NF, FERR, and/or PERR are set within the same clock cycle. The Rev. 1.30 HT46RU25/HT46CU25 RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR reg- ister, and if the RXR register has no data available. ...
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... STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to 1 two stop bits are Rev. 1.30 HT46RU25/HT46CU25 used, if the bit is equal to 0 then only one stop bit is used. PRT This is the parity type selection bit. When this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected ...
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... If this bit is equal to 1 and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal Rev. 1.30 HT46RU25/HT46CU25 to 0 and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device. ...
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... Baud Rates for BRGH=0 f =7.159MHz f =4MHz SYS SYS Kbaud Error BRG Kbaud 207 0.300 1.203 0.23 51 1.202 2.38 -0.83 25 2.404 4.863 1.32 12 4.808 9.322 -2.9 6 8.929 18.64 -2.9 2 20.83 37.29 -2.9 1 55.93 -2.9 0 62.5 111.86 -2.9 36 HT46RU25/HT46CU25 f SYS 1 (BRx64) 8000000 1 12.0208 x ( 9600 64 ) 9615 f =3.579545MHz SYS Error BRG Kbaud Error 0.00 185 0.300 0.00 0.16 46 1.19 -0.83 0.16 22 2.432 1.32 0.16 11 4.661 -2.9 -6.99 5 9.321 -2.9 8.51 2 18.643 -2 ...
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... The fol- lowing table shows various formats for data trans- mission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. 37 HT46RU25/HT46CU25 f =3.579545MHz SYS Error BRG Kbaud Error 0 ...
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... The TX output pin will then return to having a normal general purpose I/O pin function. Rev. 1.30 HT46RU25/HT46CU25 Transmitting data Stop When the UART is transmitting data, the data is Bit shifted on the TX pin from the shift register, with the least significant bit first ...
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... Setup the BRG register to select the desired baud rate. Rev. 1.30 HT46RU25/HT46CU25 Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. At this point the receiver will be enabled which will begin to look for a start bit ...
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... RXIF bit. Data will be transferred from the Shift register to the RXR register. Rev. 1.30 HT46RU25/HT46CU25 No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation ...
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... Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the par- ity enable bit to zero. Rev. 1.30 HT46RU25/HT46CU25 Bit 9 if BNO=1, ADDEN Bit 8 if BNO ...
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... Bus function: enable or disable LVR selection. LVR has enable or disable options Rev. 1.30 HT46RU25/HT46CU25 Options , the PC6 and PC7 will be used as oscillator pins means the clock source selected by options ...
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... The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.30 HT46RU25/HT46CU25 C1, C2 0pF 10pF 0pF ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.30 HT46RU25/HT46CU25 Description 44 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.30 HT46RU25/HT46CU25 Description 45 Instruction Flag Cycle Affected 2 None (2) 1 ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.30 PDF PDF PDF addr PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.30 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.30 Program Counter+1 PDF PDF PDF addr PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.30 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.30 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.30 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.30 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.30 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.30 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.30 PDF PDF PDF HT46RU25/HT46CU25 March 9, 2007 ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Rev. 1.30 HT46RU25/HT46CU25 Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 March 9, 2007 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 1.30 HT46RU25/HT46CU25 Dimensions in mil Min. Nom. 395 291 8 720 Max. 420 299 12 730 March 9, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.30 HT46RU25/HT46CU25 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 61 March 9, 2007 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.30 HT46RU25/HT46CU25 Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 62 March 9, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 HT46RU25/HT46CU25 63 March 9, 2007 ...