HT46RU25 Holtek Semiconductor Inc., HT46RU25 Datasheet - Page 25

• Manufacturer Part Number: HT46RU25
• Description: Ht46ru25/ht46cu25 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the
START bit is set from 0 to 1 .
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified,
otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START
bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note
that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required.
Rev. 1.30
Bit No.
Bit No.
PCR2
2~6
0
1
7
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
ADCS0
ADCS1
START Starts the A/D conversion. (0 1 0= start; 0 1= Reset A/D converter and set EOCB to 1 )
EOCB
Label
Label
ACS0
ACS1
ACS2
PCR0
PCR1
PCR2
TEST
PCR1
0
0
1
1
0
0
1
1
Selects the A/D converter clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
Unused bit, read as 0
For test mode use only
Defines the analog channel select
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption.
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, other-
wise the EOCB flag may have an undefined condition. See Important note for A/D initialization .
PCR0
0
1
0
1
0
1
0
1
PB7
PB7
PB7
PB7
PB7
PB7
PB7
AN7
7
PB6
PB6
PB6
PB6
PB6
PB6
PB6
AN6
ACSR (27H) Register
ADCR (26H) Register
6
Port B Configuration
AN5
AN5
PB5
PB5
PB5
PB5
PB5
PB5
25
5
Function
Function
AN4
AN4
AN4
PB4
PB4
PB4
PB4
PB4
4
PB3
PB3
PB3
PB3
AN3
AN3
AN3
AN3
3
HT46RU25/HT46CU25
PB2
PB2
PB2
AN2
AN2
AN2
AN2
AN2
2
PB1
PB1
AN1
AN1
AN1
AN1
AN1
AN1
1
March 9, 2007
AN0
AN0
AN0
AN0
AN0
AN0
AN0
PB0
0