HT37Q70 Holtek Semiconductor Inc., HT37Q70 Datasheet
HT37Q70
Related parts for HT37Q70
HT37Q70 Summary of contents
Page 1
... Technical Document Tools Information FAQs Application Note HA0075E MCU Reset and Oscillator Circuits Application Note Features Operating voltage: 3.6V~5.5V (HT37Q70/60) 3.3V~5.5V (HT37Q50/40) 2.4V~5.5V (HT37Q30/20) Operating frequency: typical 11.059MHz Oscillation modes for the Oscillator clock f : Crystal (11.059MHz) OSC 1-pin RC oscillation typ. 11.059MHz Built-in 8-bit MCU (HT-8) with 320 8 bits RAM ...
Page 2
... Block Diagram Pin Assignment Rev. 1.00 HT37Q70/60/50/40/30/20 2 February 17, 2009 ...
Page 3
... Pin Assignment HT37Q70/60 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 HT37Q70/60/50/40/30/20 2 Chip size: 2325 5155 ( m) 3 February 17, 2009 ...
Page 4
... HT37Q50/40 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 HT37Q70/60/50/40/30/20 2 Chip size: 2325 4070 ( m) 4 February 17, 2009 ...
Page 5
... HT37Q30 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 HT37Q70/60/50/40/30/20 2 Chip size: 2360 3325 ( m) 5 February 17, 2009 ...
Page 6
... HT37Q20 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 HT37Q70/60/50/40/30/20 2 Chip size: 2230 2735 ( m) 6 February 17, 2009 ...
Page 7
... Rev. 1.00 HT37Q70/60/50/40/30/20 Y Pad No. 531.665 26 386.650 27 481.650 630.665 28 584.650 729.665 29 745.620 899.560 30 847.745 999.560 1099.560 31 1012.900 32 1012.900 1206.810 33 1012.900 1311.415 34 1012.900 1412.145 35 1012.900 1568.917 1685.445 36 1012 ...
Page 8
... HT37Q20 Pad No 957.220 2 966.120 3 966.120 4 966.120 5 966.120 6 966.120 7 966.120 8 964.415 9 964.415 10 964.415 11 962.015 12 647.840 13 534.220 14 427.120 Rev. 1.00 HT37Q70/60/50/40/30/20 Y Pad No. 306.920 21 1031.340 207.920 22 1031.340 102.485 23 1031.340 24 1031.340 69.700 25 1031.340 156.700 26 1031.340 243.700 27 1031.340 336.210 28 1031.340 442.465 537.520 29 1031.340 30 1031.340 688.142 804 ...
Page 9
... Pad Description HT37Q70, HT37Q60, HT37Q50, HT37Q40 Configuration Pad Name I/O Option VDD VDD_DAC VDD_AMP VSS VSS_DAC VSS_AMP PA0~PA4 PA5/INT Pull-high I/O PA6/TMR0 Wake-up PA7/TMR1 PB0~PB7 I/O Pull-high PC0/K0~ I/O Pull-high PC7/K7 PD0/RCOUT PD1/RR I/O Pull-high PD2/RC PD3/CC RCH O SP1, SP0 O AUD_IN I VBIAS O RES I OSC1 I Crystal or RC ...
Page 10
... Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors. 3. Because the two timers are used by MIDI the external timer pin functions are disabled. Rev. 1.00 HT37Q70/60/50/40/30/20 Function Positive digital power supply Positive DAC circuit power supply Positive power Amp ...
Page 11
... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 HT37Q70/60/50/40/30/20 Function Positive digital power supply Positive DAC circuit power supply ...
Page 12
... Rev. 1.00 HT37Q70/60/50/40/30/20 Test Conditions Min. V Conditions DD f =11.059MHz for OSC 2.4 HT37Q30/20 f =11.059MHz for OSC 3.3 HT37Q50/40 f =11.059MHz for OSC 3.6 HT37Q70/ load, f =8MHz~12.8MHz, OSC 5V DAC disable 3V No load, system HALT, WDT disable load, system HALT, WDT enable ...
Page 13
... Watchdog Oscillator Period WDTOSC t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Low Voltage Width to Reset LVR Note 1/f SYS SYS SYS OSC Characteristics Curves Rev. 1.00 HT37Q70/60/50/40/30/20 Test Conditions Min. V Conditions DD 2.4V~5.5V 8000 3.3V~5.5V 8000 3.6V~5.5V 8000 Power-up or wake-up from HALT 0.25 13 Ta=25 C Typ ...
Page 14
... Output Power R =8W, V =1kHz Sinewave for 3.0V LOAD IN R =8W, V =1kHz Sinewave for 5.0V LOAD IN Rev. 1.00 HT37Q70/60/50/40/30/20 14 February 17, 2009 ...
Page 15
... The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one Rev. 1.00 HT37Q70/60/50/40/30/20 instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cy- cles, the pipelining structure of the microcontroller en- sures that instructions are effectively executed in one instruction cycle ...
Page 16
... Instruction code address bits BP1.4~BP1.0: ROM bank pointer S17~S0: Stack register bits For the HT37Q70/60, the Program Counter is 18 bits wide, i.e. from b17~b0. For the HT37Q50/40, the Program Counter is 17 bits wide, i.e. from b16~b0, therefore the b17 column in the table is not applicable. ...
Page 17
... Structure The Program Memory has a capacity of 256K by 16, 192K by 16, 128K by 16, 96K by 16, 64K 32K by Rev. 1.00 HT37Q70/60/50/40/30/20 16 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and ROM bank point, and also contains general data, Wave table data, table information and interrupt entries ...
Page 18
... Rev. 1.00 HT37Q70/60/50/40/30/20 Program Memory Structure 18 February 17, 2009 ...
Page 19
... TBHP1_1~TBMP1_5: TBHP1 (bit 1 ~0) to TBMP1 (bit7 ~5) BP1_4 ~BP1_0: Bits of bank BP1 bit0~4 For the HT37Q70/60, the Table address location is 18 bits wide, i.e. from b17~b0. For the HT37Q50/40, the Table address location is 17 bits wide, i.e. from b16~b0. For the HT37Q30, the Table address location is 16 bits wide, i.e. from b15~b0. ...
Page 20
... HT37Q70/60/50/40/30/20) romsumvalue1 .section at 1F00h code dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.00 HT37Q70/60/50/40/30/20 20 February 17, 2009 ...
Page 21
... Select ROM Bank30 (3C000h~3DFFFh) 00011111b= Select ROM Bank31 (3E000h~3FFFFh) Note: For the HT37Q70/60, the ROM bank point register is 5 bits wide effectively, i.e. from b4~b0. For the HT37Q50/40, the ROM bank point register is 4 bits wide effectively, i.e. from b3~b0. For the HT37Q30, the ROM bank point register is 3 bits wide effectively, i.e. from b2~b0. ...
Page 22
... Spe- cial Function Register section. Note that for locations Rev. 1.00 HT37Q70/60/50/40/30/20 that are unused, any read instruction to these addresses will return the value 00H . Although the Special Pur- pose Data Memory registers are located in Bank 0, they will still be accessible even if the Bank Pointer has se- lected Bank 1 ...
Page 23
... Set dacc.7 ; access data to iar1 by MP2 CLR rBP2 ; clear RAM bank pointer 2 Rev. 1.00 HT37Q70/60/50/40/30/20 access data from both Bank 0 and Bank 1. Using MP1 or MP2 are selected by DACC.7. As the Indirect Ad- dressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indi- rectly will result in no operation ...
Page 24
... Unused bit RBP2 (2FH) Note: Using MP1 or MP2 are selected by DACC.7. Rev. 1.00 HT37Q70/60/50/40/30/20 Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. ...
Page 25
... C is cleared also affected by a rotate through carry instruction. Rev. 1.00 HT37Q70/60/50/40/30/ set if an operation results in a carry out of the low nibbles in addition borrow from the high nib- ble into the low nibble in subtraction; otherwise AC is cleared ...
Page 26
... Wavetable Function Registers - CHANNEL_NUMBER, FREQ_NUMBER_H, FREQ_NUMBER_L, REPEAT_NUMBER_H, REPEAT_NUMBER_L, VOLUME_CONTROL, L_VOL, R_VOL HT37Q70/60/50/40/30/20 contains Wavetable synthe- sizer Function. The HT37Q70/60/50/40/30/20 has a built-in 8 output channels. CHANNEL_NUMBER is channel number selection. FREQ_NUMBER_H and FREQ_NUMBER_L are used to define the output speed of the PCM file. START_ADDRESS_H and START_ADDRESS_L is setup for the start address of the PCM code before Wavetable function implement ...
Page 27
... PA7 can be selected individually to have this wake-up feature using an PA wake up option, located in the con- figuration. Rev. 1.00 HT37Q70/60/50/40/30/20 I/O Port Control Registers Each I/O port have their own control register, known as PAC, PAB, PCC and PDC, which control the input/out- put configuration. With this control register, each PA~PD I/O pin with or without pull-high resistors can be recon- figured by pull-hi option control ...
Page 28
... CR/F analog switch Inputs The HT37Q70/60/50/40/30 have 8 CR/F converter in- puts. All of these analog inputs are pin-shared with PC0 to PC7. If these pins are to be used as CR/F ana- log switch Inputs and not as normal I/O pins then the corresponding bits in the Option, PC0~7 share pin configuration . The HT37Q20 have 4 CR/F converter inputs ...
Page 29
... Timer/Event Counter 0 Structure 8-bit Timer/Event Counter 1 Structure Rev. 1.00 HT37Q70/60/50/40/30/20 initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and deter- mines how the timer used ...
Page 30
... FFFFH for the 16-bit timers, at which point the timer overflows and a timer internal interrupt signal is Timer/Event Counter 0 Control Register Rev. 1.00 HT37Q70/60/50/40/30/20 generated. The timer value will then be reset with the ini- tial preload register value and continue counting. Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, the preload registers must first be cleared to all zeros ...
Page 31
... Timer/Event Counter 1 Control Register Rev. 1.00 HT37Q70/60/50/40/30/20 Timer Counter 2 Control Register 31 February 17, 2009 ...
Page 32
... TMR0C.5. The input clock frequency of 8 bit timer to the timer is Fosc divided by the value pro- grammed into the timer prescaler, the value of which is Rev. 1.00 HT37Q70/60/50/40/30/20 determined by bits PSC0~PSC2 of the TMR1C~ TMR2C register. The timer-on bit, TON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one ...
Page 33
... PA6/TMR0 or PA7/TMR1 pin and not by the logic level. Pulse Width Measure Mode Timing Diagram Rev. 1.00 HT37Q70/60/50/40/30/20 Prescaler Bits PSC0~PSC2 of the TMRC1~ TMRC2 registers can be used to define the pre-scaling stages of the internal clock sources of the Timer/Event Counter. ...
Page 34
... Rev. 1.00 HT37Q70/60/50/40/30/20 register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction ...
Page 35
... Also when an interrupt occurs, the corresponding re- quest flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Rev. 1.00 HT37Q70/60/50/40/30/20 /8 0.7234 s OSC /32 2.89 s OSC /16 1 ...
Page 36
... Suitable masking of the individual interrupts using the INTC register can pre- vent simultaneous occurrences. Interrupt Low Byte Control Register Rev. 1.00 HT37Q70/60/50/40/30/20 Interrupt Source Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow ...
Page 37
... Interrupt High Byte Control Register Rev. 1.00 HT37Q70/60/50/40/30/20 Interrupt Structure 37 February 17, 2009 ...
Page 38
... The related interrupt request flag, RCOCF, will be reset and the EMI bit cleared to disable further interrupts. Rev. 1.00 HT37Q70/60/50/40/30/20 ADPCM Interrupt The internal ADPCM interrupt is initialized by setting the ADPCM interrupt request flag (ADPCMF: bit 6, CH0F: bit 3 and CH1F: bit 7 of INTCH).The CH0F and CH1F set by ADR0 or ADR1 empty respectively ...
Page 39
... RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period Rev. 1.00 HT37Q70/60/50/40/30/20 to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage ...
Page 40
... SST WDT Time-out Reset during Power Down Timing Chart Rev. 1.00 HT37Q70/60/50/40/30/20 Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer ...
Page 41
... RepH RepL ENV Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 42
... TMRBL RCOCR 0 0 Note: u stands for unchanged x stands for unknown stands for unimplemented Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 43
... RepH RepL ENV Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 44
... TMRBL RCOCR 0 0 Note: u stands for unchanged x stands for unknown stands for unimplemented Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 45
... RVC WDTS ADR Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 46
... TMRBL RCOCR 0 0 Note: u stands for unchanged x stands for unknown stands for unimplemented Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 47
... RVC WDTS ADR Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 48
... TMRBL RCOCR 0 0 Note: u stands for unchanged x stands for unknown stands for unimplemented Rev. 1.00 HT37Q70/60/50/40/30/20 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 49
... C1 and C2. The exact values of C1 and C2 should be selected in consultation Crystal/Resonator Oscillator Rev. 1.00 HT37Q70/60/50/40/30/20 with the crystal or resonator manufacturer s specifica- tion. The external parallel feedback resistor, Rp, is nor- mally not required but in some cases may be needed to assist with oscillation start up. ...
Page 50
... Special atten- tion must be made to the I/O pins on the device. All high-impedance input pins must be connected to either Rev. 1.00 HT37Q70/60/50/40/30/20 a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur- rent consumption. This also applies to devices which ...
Page 51
... A configuration option can select the instruction clock, which is the system clock divided the WDTclock Rev. 1.00 HT37Q70/60/50/40/30/20 source instead of the internal WDT oscillator. If the in- struction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped ...
Page 52
... Digital to Analog Converter (DACC) The two D/A converters of HT37Q70/60/50/40/30/20 are 16-bit high-resolution with excellent frequency response char- acteristics and good power consumption for mono audio output. D7 1Dh DAC High Byte B15 1Eh DAC Low Byte B7 1Fh DAC Control (DACC) BP_R Note: B15~B0 is D/A conversion result data bit MSB~LSB. ...
Page 53
... The Integrated Power Amp. The Power Amp integrated class AB mono speaker driver contained in HT37Q70/60/50/40/30.It provides property of high S/N ratio, high slew rate, low distortion, large output voltage swing, excellent power supply ripple rejection, low power consumption, low standby current and power off control etc. ...
Page 54
... BP1 value, the other is the start address of the PCM code. Rev. 1.00 HT37Q70/60/50/40/30/20 HT37Q70/60 contains ST13~ST0 is used to define the start address of each PCM code and reads the wave- form data from this location. HT37Q70/60 provides PCM 12/8 bit source PCM 12 Start address definition ...
Page 55
... ADPC 34H ADPS Rev. 1.00 HT37Q70/60/50/40/30/20 Repeat Number Definition The repeat number is used to define the address which is the repeat point of the sample. When the repeat num- ber is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80H) until the vol- ume become close ...
Page 56
... TMR4L and RCOCR. The internal timer clock is the in- put clock source for TMRAH and TMRAL, while the ex- Rev. 1.00 HT37Q70/60/50/40/30/20 ternal RC oscillator is the clock source input to TMRBH and TMRBL. The OVB bit, which is bit 0 of the RCOCR register, decides whether the timer interrupt is sourced from either the Timer A overflows or Timer B overflow ...
Page 57
... Clear External RC Oscillation Converter interrupt request flag ; Program continue Rev. 1.00 HT37Q70/60/50/40/30/20 RCOCR Register directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first ...
Page 58
... Analog Switch There are 8 analog switch lines in the microcontroller for K0~K7 for HT37Q70/60/50/40/30, except HT37Q20 which only have 4 analog switch lines for K0~K3 and the Analog Switch control register, which is mapped to the data memory. All of these Analog Switch lines can be used for touch key input keys. ...
Page 59
... Function : enable or normal I/O (PD Analog Switch: enable or normal I/O (PC) K0 Enable and PC1~7 K0~1 Enable and PC2~7 K0~2 Enable and PC3~7 10 K0~3 Enable and PC4~7 K0~4 Enable and PC5~7 K0~5 Enable and PC6~7 K0~6 Enable and PC7 K0~7 Enable Rev. 1.00 HT37Q70/60/50/40/30/20 Function / OSC OSC 59 February 17, 2009 ...
Page 60
... HT37Q20 can t apply the internal power amplifier circuit application because it don t integrated power amplifier. User need use external power amplifier circuit with HT37Q20 application circuit, the RCH pin connect internal power amplifier circuit or external power amplifier circuit individually. Rev. 1.00 HT37Q70/60/50/40/30/20 60 February 17, 2009 ...
Page 61
... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT37Q70/60/50/40/30/20 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
Page 62
... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT37Q70/60/50/40/30/20 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
Page 63
... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT37Q70/60/50/40/30/20 Description 63 Cycles Flag Affected ...
Page 64
... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 HT37Q70/60/50/40/30/20 64 February 17, 2009 ...
Page 65
... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 HT37Q70/60/50/40/30/20 addr 65 February 17, 2009 ...
Page 66
... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1.00 HT37Q70/60/50/40/30/ February 17, 2009 ...
Page 67
... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 HT37Q70/60/50/40/30/20 addr 67 February 17, 2009 ...
Page 68
... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 HT37Q70/60/50/40/30/20 Stack Stack Stack [m]. 0~6) 68 February 17, 2009 ...
Page 69
... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 HT37Q70/60/50/40/30/20 [m]. 0~6) 69 February 17, 2009 ...
Page 70
... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 HT37Q70/60/50/40/30/20 [ February 17, 2009 ...
Page 71
... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 HT37Q70/60/50/40/30/20 0 [m] [ February 17, 2009 ...
Page 72
... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 HT37Q70/60/50/40/30/20 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 72 February 17, 2009 ...
Page 73
... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 HT37Q70/60/50/40/30/20 73 February 17, 2009 ...
Page 74
... Package Information 20-pin SOP (300mil) Outline Dimensions MS-013 Symbol Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mil Min. Nom. 393 256 12 496 Max. 419 300 20 512 104 February 17, 2009 ...
Page 75
... SOP (300mil) Outline Dimensions MS-013 Symbol Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mil Min. Nom. 393 256 12 697 Max. 419 300 20 713 104 February 17, 2009 ...
Page 76
... SSOP (300mil) Outline Dimensions Symbol Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 February 17, 2009 ...
Page 77
... QFP (14mm´20mm) Outline Dimensions Symbol Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mm Min. Nom. 18.8 13.9 24.8 19.9 1 0.4 2.5 0.1 1.15 0 Max. 19.2 14.1 25.2 20.1 3.1 3.4 1.45 0.2 7 February 17, 2009 ...
Page 78
... LQFP (10mm´10mm) Outline Dimensions Symbol Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mm Min. Nom. 11.9 9.9 11.9 9.9 0.4 0.16 1.35 0.1 0.45 0 Max. 12.1 10.1 12.1 10.1 1.45 1.6 0.75 0.2 7 February 17, 2009 ...
Page 79
... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 24.8 30.2 0.2 Dimensions in mm 330.0 1.0 100.0 0.1 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 32.2 38.2 0.2 79 February 17, 2009 ...
Page 80
... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mm +0.3/-0.1 24.0 12.0 0.1 1.75 0.10 11.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.30 0.05 21.3 0.1 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.10 11.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2 ...
Page 81
... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT37Q70/60/50/40/30/20 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.10 14.2 0.1 2 Min. +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 12.0 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 0.1 81 February 17, 2009 ...
Page 82
... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT37Q70/60/50/40/30/20 82 February 17, 2009 ...