PI6C48533-01 Pericom Semiconductor Corporation, PI6C48533-01 Datasheet

no-image

PI6C48533-01

Manufacturer Part Number
PI6C48533-01
Description
3.3v Low Skew 1-to-4 Differential/lvcmos To Lvpecl Fanout Buffer
Manufacturer
Pericom Semiconductor Corporation
Datasheet
Features
Block Diagram
CLK_SEL
CLK_EN
Pin-to-pin compatible to ICS8533-01
Maximum operation frequency: 800MHz
4 pair of differential LVPECL outputs
Selectable differential CLK and PCLK inputs
CLK,
SSTL and HCSL input level
PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
Output Skew: 100ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2ns (maximum)
3.3V power supply
Operating Temperature: -40
Packaging (Pb-free & Green avaliable):
-20-pin TSSOP (L)
n
PCLK
PCLK
n
CLK
CLK
n
CLK pair accepts LVDS, LVPECL, LVHSTL,
0
1
o
C to 85
D
LE
o
Q
C
Q
n
Q
n
Q
n
Q
n
Differential/LVCMOS to LVPECL Fanout Buffer
Q
Q
Q
Q
0
1
2
3
0
1
2
3
1
Description
The PI6C48533-01 is a high-performance low-skew LVPECL fanout
buffer. PI6C48533-01 features two selectable differential inputs and
translates to four LVPECL ultra-low jitter outputs. The inputs can
also be configured to single-ended with external resistor bias circuit.
The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or
HCSL signals, and PCLK input accepts LVPECL or SSTL or CML
signals. The outputs are synchronized with input clock during asyn-
chronous assertion/deassertion of CLK_EN pin. PI6C48533-01 is
ideal for differential to LVPECL translations and/or LVPECL clock
distribution. Typical clock translation and distribution applications
are data-communications and telecommunications.
Pin Diagram
CLK_SEL
CLK_EN
n
PCLK
PCLK
n
CLK
CLK
V
V
NC
NC
CC
EE
1
2
3
4
5
6
7
8
9
10
3.3V Low Skew 1-to-4
20
19
18
17
16
15
14
13
12
11
PI6C48533-01
Q
n
V
Q
n
Q
n
V
Q
n
Q
Q
Q
Q
PS8737B
CC
CC
0
1
2
3
0
1
2
3
02/08/06

Related parts for PI6C48533-01

PI6C48533-01 Summary of contents

Page 1

... CLK_SEL Differential/LVCMOS to LVPECL Fanout Buffer Description The PI6C48533- high-performance low-skew LVPECL fanout buffer. PI6C48533-01 features two selectable differential inputs and translates to four LVPECL ultra-low jitter outputs. The inputs can also be configured to single-ended with external resistor bias circuit. The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL or CML signals ...

Page 2

... Selected Source CLK, CLK n PCLK, PCLK n CLK, CLK n PCLK, PCLK n 2 3.3V Low Skew 1-to-4 Description Min. Typ. Max Outputs Diasbled: Low Diasbled: High Disabled: Low Disabled: High Enabled Enabled Enabled Enabled PI6C48533-01 x Units pF KΩ PS8737B 02/08/06 ...

Page 3

... CC /2 HIGH LOW Single Ended to Differential CC HIGH LOW Single Ended to Differential LOW HIGH Single Ended to Differential Conditions Referenced to GND Referenced to GND Referenced to GND 3 PI6C48533-01 3.3V Low Skew 1-to-4 Polarity None Inverting None Inverting None Inverting None Inverting Inverting Inverting Min. Typ. Max. 4.6 -0.5 V +0. ...

Page 4

... 3.6V ( 3.3V Low Skew 1-to-4 Min. Typ. 3.0 3.3 -40 = 3.0V to 3.6V unless otherwise stated.) Min. Typ. 2 -0.3 -5 -150 Min. Typ -150 = 0V -5 0.15 V +0.5 EE +0.3V CC PI6C48533-01 Max. Units 3 Max. Units V +0 0.8 150 5 µA Max. Units 5 uA 150 1 0.85V ...

Page 5

... 3. PCLK V = 3.6V 3.6V (1,2) PCLK 50Ω 3.0V to 3.6V Conditions (3) 20% - 80% 5 PI6C48533-01 3.3V Low Skew 1-to-4 Min. Typ. Max. 5 150 = 0V -150 = 0.6 1.0 +0.3V 2V, unless otherwise stated below. CC Min. Typ. ...

Page 6

... R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. DD Single Ended Figure 2: Single-ended Signal Driving Differential Input Differential/LVCMOS to LVPECL Fanout Buffer Clock Input C1 R2 0.1µ PI6C48533-01 3.3V Low Skew 1-to CLK1 nCLK1 PS8737B 02/08/06 ...

Page 7

... Package Code L 7 PI6C48533-01 3.3V Low Skew 1-to-4 ���� ���� ����� ���� ���� ...

Related keywords