AMD-766 Advanced Micro Devices, AMD-766 Datasheet
AMD-766
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AMD-766 Summary of contents
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... March 2001 Peripheral Bus Controller Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet TM AMD-766 Data Sheet 1 ...
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... Trademarks AMD, the AMD logo, and combinations thereof, and AMD-766 are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...
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... Transitions Between MOFF/SOFF/STD/STR and FON .......................................................... 27 4.6.1.5.2 Transitions From FON To C2, C3 And POS........................................................................... 28 4.6.1.5.3 Transitions From C2, C3 And POS To FON........................................................................... 28 4.6.2 Serial IRQ Protocol .......................................................................................................................... 29 4.6.3 SMBus Controller ............................................................................................................................ 29 4.6.4 Plug And Play .................................................................................................................................. 30 4.6.5 General Purpose IO .......................................................................................................................... 30 5 Registers ...............................................................................................................................31 5.1 Register Overview .....................................................................................................................31 Preliminary Information AMD-766 Table of Contents TM Peripheral Bus Controller Data Sheet 3 ...
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... Electrical Data......................................................................................................................88 6.1 Absolute Ratings........................................................................................................................88 6.2 Operating Ranges......................................................................................................................88 6.3 DC Characteristics ....................................................................................................................88 6.4 Power dissipation.......................................................................................................................89 6.5 Switching Characteristics ..........................................................................................................89 7 Pin Designations...................................................................................................................89 8 Package Specification...........................................................................................................92 9 Test .......................................................................................................................................93 9.1 High Impedance Mode ..............................................................................................................93 9.2 NAND Tree Mode .....................................................................................................................93 10 Appendixes ........................................................................................................................95 10.1 Appendix A: Glossary ..............................................................................................................95 10.2 Appendix B: References ...........................................................................................................95 10.3 Appendix C: Conventions.........................................................................................................96 Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 4 ...
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... March 2001 1 Overview The AMD-766 peripheral bus controller Southbridge component of personal computer chipsets. The AMD-766 peripheral bus controller (the IC) connects to a host memory controller through the PCI bus. 1.1 Features PCI interface (PCI specification revision 2.2 compliant). LPC bus to connect peripherals such as super IO and BIOS ...
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... Legacy programmable interrupt controller IOAPIC C Case Temperature C = Commercial temperature range Package Type A = Plastic Ball Grid Array Family/Core AMD-766 Peripheral Bus Controller Data Sheet Four USB ports Primary IDE port Secondary IDE port ISA bus LPC bus DMA signals 32-KHz oscillator ...
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... S3:S5” provides the state of the pin while in the suspend to disk, suspend to RAM, or soft off system sleep states. “Func” means that the signal is active or functional, operating per its defined function. “Last State” indicates that the signal remains in the state that it was in when the system entered POS. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 7 ...
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... PCI bus writes from the IC to system memory are visible to the host. See section 4.3.2 for more details. This signal requires an external pull-up resistor with a value between 10K to 200K ohms. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type IO IO ...
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... LPC bus. KA20G. Keyboard A20 gate. This is designed to be the gate A20 signal from the system keyboard controller. It affects A20M#. KBRC#. Keyboard reset command. This is designed to be the processor Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type Output VDD3 Input ...
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... DIOR[P,S]#. Output; IDE controller [primary, secondary] port IO read command. DIOW[P,S]#. Output; IDE controller [primary, secondary] port IO write command. DRDY[P,S]. Input; IDE controller [primary, secondary] port ready strobe. Input Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type Output VDD3 IO Input ...
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... SD pins. Therefore, the outputs of the latches may be software-controlled flags. FLAGWR is asserted during writes to PM18. This pin may also be configured as GPIO10 by PMCA. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type Output, IO ...
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... C3A4C. PWRBTN#. Power button. This may be used to control the automatic transition from a sleep state to FON. It controls PM00[PWRBTN_STS]. Also asserted for four seconds from any state other than SOFF, then Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type IO Output, ...
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... SUSPEND#. Suspend output. This may be used during the POS state to control an external power planes controlled by C3A50. THERM#. Input; thermal warning detect. This may be used to automatically enable processor throttling as specified by C3A50[TTH_EN, TTH_RATIO]. See section 4.6.1.4 for more details. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type Input w/H OD ...
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... VDD_USB. 3.3 volt supply filtered for the USB transceivers. This plane is required to be valid in all power states except MOFF. VSS. Main ground plane. VSS_USB. Ground plane filtered for the USB transceivers. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet IO cell type Input Input ...
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... Various system resets may be initiated through PORTCF9 also possible to reset the processor (without clearing the cache) with an INIT interrupt through the keyboard controller via KBRC#, the PORT92 register, or from a PCI-defined shutdown special cycle from the host. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15 ...
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... MEMW# pulses are not generated for these cycles. MEMR#/MEMW# pulses are always generated for BIOS- address transactions as specified by C0A43. The default pulse width for 8-bit IO commands to the ISA bus is 6 BCLKs. The default pulse width for 16-bit IO commands to the ISA bus is 3 BCLKs. Preliminary Information AMD-766 & ~C0A48[DMAEN#] & ~C0A48[IDEEN#] & ~C0A48[IUSBEN#] | CONFIG_SPACE_0 TM ...
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... The IC includes the following legacy support logic: PORT61 and PORT92 legacy registers. FERR# and IGNNE interrupt logic. PORT4D0 legacy interrupt edge-level select logic. PORTCF9 reset logic. Legacy DMA controller. Legacy programmable interval timer. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 17 ...
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... PIRQD# is left in the high impedance state. So the USB interrupt is wired-ORed into the active state with external interrupts on PIRQD#. The result enters the IC and goes to the interrupt routing logic. The following are the interrupt routing logic equations: Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Interrupt pins to the host Legacy ...
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... From the above equations, a few details can be derived: When a PCI, PNP, or SCI interrupt is enabled onto a PIC_IRQ, then the ISA and serial IRQ capability for the IRQ is disabled. External IRQs and serial IRQs are designed to be edge triggered. Preliminary Information AMD-766 PIRQA# PIRQB# PIRQC# PIRQD# == 4’ ...
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... It is expected that the memory controller enables the line for three PCLK cycles. WSC# is required to be driven high for at least one clock before it is allowed to be driven low again. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Message is sent 20 ...
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... OHCI-defined register HcControl_InterruptRouting. See section 4.3.4.1 for data on routing keyboard and mouse emulation interrupts. SMI interrupts are also generated in response to accesses to IO ports 60h and 64h and to IRQ1 and IRQ12 in support of the emulation logic. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet APIC IRQ Connection 12 PIC_IRQ12 ...
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... SIT_EN, where the events may be enabled to reload the system inactivity timer, and the resume columns which show where the registers to enable the resume events from C2, C3, POS, STD, STR, and SOFF to FON. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 22 ...
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... Real time clock IRQ PM00 PWRBTN# pin PM00 EXTSMI# pin PM20 PME# pin PM20 RI# pin PM20 SLPBTN# pin PM00 THERM# pin PM20 Preliminary Information AMD-766 Event SCI/SMI SMI only EVT in PM28 EN SMI_EN in PM2A SMB_EVT PME2 SMBUS_EN PME2 PME2 PME2 TRP_EVT PMAC ...
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... PMA8 provides the status registers for these and several fixed-address traps. These traps are generated for the specified transactions that are presented to the host PCI bus. They may be enabled to generate ACPI interrupts through PMAC or SMI interrupts through PM2A. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet OR AND- OR ...
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... C3A50. Snoop-capable clock control (C2). In C2, the processor is placed into the stop-grant state. Signal control during C2 is specified by C3A50 expected that the processor’s cache may be snooped while in this state. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet VDD3 VDD_AUX On ...
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... RPWRON low VDD_AUX power applied and C3A43[G3TOS5]=1 MOFF mechanical off VDD_AUX power applied and C3A43[G3TOS5]=0 Power failure Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet CPU initiated (PM14) FON full on Resume event PWRON#, RPWRON asserted CPU initiated (PM15) Resume event CPU initiated (PM04) ...
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... FON to SOFF/STD/STR For transitions to SOFF that are initiated by a power/sleep button override event or by PORTCF9[FULLRST], the STPCLK# assertion and stop-grant cycles are skipped; the sequence starts with the assertion of DCSTOP#. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet More than ...
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... CPUSTOP#, CPUSLEEP, and DCSTOP# pins is not enabled in C3A50: CACHE_ZZ. At least 4 PCLK cycles after the resume event, CACHE_ZZ is deasserted. If resuming from POS and C3A50[APIC_POSEN] is low, then PICCLK becomes active at this time. STPCLK PCLK cycles after CACHE_ZZ, STPCLK# is deasserted. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 28 ...
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... If the SMBus host controller detects this address for a read cycle with PME2[CYCTYPE] set to receive byte (001b), then it stores the address returned by the SMBALERT# slave in PME6[7:0]. If bits[7:1] of this address are 1111_0xxb, indicating a 10-bit address, then it stores the next byte from the slave in PME6[15:8]. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 29 ...
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... The output of the two GPIO output clocks may be selected to drive the output of any of the GPIO pins. They may be used to blink LEDs or for other functions. Preliminary Information TM AMD-766 DEBOUNCE Latch Vcc Q D Debounce Circuit 1 LE ...
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... PCI configuration spaces. Function Mnemonic Function 0 C0Axx PCI-ISA/LPC bridge 1 C1Axx IDE controller 2 C2Axx Not used 3 C3Axx System management registers 4 C4Axx USB controller Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 31 ...
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... RESET# must be asserted in order to clear the bit. Write once After RESET#, these registers may be written to once. After they are written, they become read only until the next RESET# assertion. Preliminary Information TM AMD-766 Type Function Slave DMA controller Master interrupt controller Programmable interval timer ...
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... C0A2C: PCI-ISA Bridge Subsystem ID and Subsystem Vendor ID Register Configuration space; function 0; offset: 2F-2Ch. Default: 0000_0000h. Read only. 31:16 SSID SSVENDORID and SSID. Subsystem vendor ID and subsystem ID registers. This register is write accessible through C0A70. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 VID 15:0 COMMAND[15:0] 15:8 LATENCY ...
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... LPC_IOR. LPC IO recovery recovery delay (specified by IORT) enforced for both LPC and legacy IO cycles. 0=IO recovery delay only enforced for legacy IO cycles (cycles to the DMA controller, legacy PIC, programmable interval timer, and real-time clock). Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet ...
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... P92FR. Port 92 fast reset. Read-write. 1=Writes that attempt to set PORT92[0]—the fast CPU reset bit—are enabled. 0=Writes to PORT92[0] are ignored. MBL. Must be low. Read-write. This bit is required to be low at all times; otherwise undefined behavior will result. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet ...
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... CPURS. CPU reset select. Read-write. 1=Processor resets are directed toward the INIT# pin. 0=Processor resets are directed toward the CPURST# pin. This bit is required to be high. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Address translation for ISA bus[23:0] FC_0000 - FC_7FFFh ...
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... PCI bus is granted to the IC expected that this bit is normally low. Note: When C0A47[PCIDTEN]=0, the state of C0A4A[PGNT1ST] is ignored and the IC always waits for the PCI bus to be granted to the LPC DMA/master state machine before asserting the DACK# signal to DMA controller. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 4:3 2 SUB ...
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... ISA. If USB keyboard emulation is enabled, these cycles are routed to the USB block. ACPI. ACPI controller ports 62h and 66h are routed to LPC. 0=These accesses are routed to the ISA bus. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 4:3 2 ...
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... MSEN. MSS enable. 1=MSS IO port accesses specified by the MSRANGE field in this register are routed to the LPC bus. 0=These accesses are routed to the ISA bus. SIO. Super IO configuration. 1=Super IO configuration IO ports, 2Eh - 2Fh, are routed to the LPC bus. 0=These accesses are routed to the ISA bus. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 3 2:0 SAEN SARANGE ...
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... FFF(x)_0000h]. C0A88 includes 8 four-bit lock registers, OARx where x ranges as [ 0]; each four-bit register controls an 8Kbyte address range as follows: [FFBF_(x+1)FFFh: FFBF_(x)000h]. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 4 3:0 GP1EN ...
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... LKLOCK. SMM access to the ROM access registers lock. Read; write 1 only. This bit may only be set high by software cleared by PCIRST#. 0=Write access to C0A80/C084/C0A88/C0A8C and C0A43 always enabled. 1=Write access to C0A80/C084/C0A88/C0A8C and C0A43 only enabled in SMM mode (see C0A80 for determination of when the system is in SMM mode). Preliminary Information TM AMD-766 23:20 19:16 15:12 OARA OAR8 ...
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... The value written to this bit is ORed with the KA20G bit from the keyboard controller and then routed to the A20M# pin. In order for this bit to control A20M#, KA20G must be low. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 4 3 ...
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... RSTCMD and SYSRST are both written high, ( power fail is detected (PWRGD goes low without the appropriate command), or (3) PM46[2NDTO_STS] is set while C3A48[NO_REBOOT]=0. 0=Full resets do not transition the system to SOFF; only the reset signals are asserted. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet FERR_CLR# FERR# 7:0 ...
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... Write transfer 10b Read transfer 11b Illegal 1:0 Channel select Note: DMA channel 4 is hard-wired into cascade mode; however cascade mode is obsolete for all other channels. Preliminary Information AMD-766 Number Comments 8 1 for each channel (0-7) (see note for each channel (0-7) (see note 1) ...
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... When this value is written, 010b is stored in the register, rate generator mode. 111b When this value is written, 011b is stored in the register, square wave mode. 0 BCD: binary coded decimal. 1=Counter specified by SC[1:0] operates in binary coded decimal. 0=Counter specified by SC[1:0] operates in 16-bit binary mode. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 45 ...
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... AEOI. Auto EOI. This bit is ignored; the IC only operates in normal EOI mode (this bit low). 0 UPM. x86 mode. This bit is ignored; the IC only operates in x86 mode (this bit high). Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Register Initialization command word 1 (ICW1) Operation command word 2 (OCW2) ...
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... P: poll command. 1=Poll enabled; next IO read of the interrupt controller treated like an interrupt acknowledge cycle. 1:0 RR (bit 1) and RIS (bit 0). Read register command. These are decoded as: [RR,RIS] = 0Xb [RR,RIS] = 10b [RR,RIS] = 11b Preliminary Information TM AMD-766 R, SL, EOI Function 100b 101b 110b 111b No action. Reset special mask mode. Set special mask mode. ...
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... RTC71. Only the lower 128 bytes of the CMOS RAM are accessible through RTC70 and RTC71. NMIDIS. NMI disable. 1=PORT61[IOCHK and SERR] are disabled from being able to generate NMI interrupts to the processor. Note: The state of this register is read accessible through C0A41[NMIDIS]. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Attribute Default Read-write 0000 0000h ...
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... STATUS[13] Received Master Abort, RMASABT. Read; set by hardware; write 1 to clear. 1=An EIDE master cycle was terminated with a master abort. STATUS[15:14]. Read only. These bits are fixed at their default values. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Range for binary mode Range for BCD mode 01-1Fh 01-0Ch ...
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... BASE BASE[31:2] Port Address. These bits specify a 4-byte IO address space that maps to the ATA-compliant control register set for the primary port (legacy IO space 3F6h). Note: Only byte 2 of this space is used. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:8 PROG I/F[7:0] 15:8 LATENCY ...
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... INTERRUPT PIN. Read only. When either C1A08[8] or C1A08[10] is high, then field reads 01h. When they are both low, it reads 00h. MIN GNT. Read only. These bits are fixed at their default values. MAX LATENCY. Read only. These bits are fixed at their default values. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 SSVENDORID 15:8 INTERRUPT PIN 2:0 Reserved ...
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... SD0RT[3:0] Secondary Drive 0 Minimum Recovery Time. SD0PW[3:0] Secondary Drive 0 Active Pulse Width. PD1RT[3:0] Primary Drive 1 Minimum Recovery Time. PD1PW[3:0] Primary Drive 1 Active Pulse Width. PD0RT[3:0] Primary Drive 0 Minimum Recovery Time. PD0PW[3:0] Primary Drive 0 Active Pulse Width. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 19:16 15:0 CABLE IDE_CONFIG 19:16 15:12 ...
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... P1, S0, S1]UDMA[7] [Primary, Secondary] Drive [1,0] Ultra DMA Mode Enable Method, [P0, P1, S0, S1]ENMODE. Read-write. 1=Enable UDMA mode by setting bit 6 of this register. 0=Enable UDMA mode by detecting the “Set Feature” ATA command. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 19:16 15:8 SXRT ...
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... IO space (base pointers: C1A20); offset: 08h. Default: 00h. 7:0 SCMD SCMD[0] Start/Stop Bus Master, STSP. Write 1 only. Reads always return zero. SCMD[2:1]. Reserved. SCMD[3] Read or Write Control, RW. Read-write. 1=Read cycles specified (read from the drive; write to system memory). SCMD[7:4]. Reserved. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 1:0 Reserved 54 ...
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... USB controller was master of the PCI bus. STATUS[13] Received Master Abort. Read; set by hardware; write 1 to clear. 1=A USB master cycle was terminated with a master abort. STATUS[15:14]. Read only. These bits are fixed at their default values. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 VID 15:0 COMMAND[15:0] ...
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... DB16: Data Buffer Region 16. 1=The size of the region for the data buffer is 16 bytes. 0=The region is 32 bytes. PIPDIS: SIE Pipelining Disable. 1=Transfer descriptors are disabled from being pipelined with USB bus activity. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:8 LATENCY ...
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... HceControl and HceStatus reset to 00h. HceInput and HceOutput are not reset. HcDoneHd[31:4] should not be modified. HcFmInterval_FSLargestDataPacket is limited to 14 bits. Bit 15 is read-only 0. HcFmNumber should not be modified. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Offset Register 34-37h HcFmInterval 38-3Bh HcFrameRemaining 3C-3Fh HcFmNumber ...
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... Configuration space; function 3; offset: 40h. Default: 00h. Read-write Reserved Reserved Reserved TH2SD. Throttling 2 second delay. 1=There is a 2.0 to 2.5 seconds delay after THERM# is asserted before thermal throttling is initiated as specified by C3A50. 0=Thermal throttling is initiated immediately after THERM# is asserted. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 VID 15:0 COMMAND[15:0] 15:8 LATENCY 15:0 SSVENDORID 4 3 ...
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... PPSTATE. Previous power state. Read only. This field holds the most previous power state from which the system entered the FON state. This field resides on the VDD_AUX power plane. This field is encoded as follows: PPSTATE Power state 0h Reserved 1h POS power on suspend Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet PBIN TMR32 NO_REBOOT STPGNT 4 3:0 GPIOSCI SCISEL 2:0 PPSTATE ...
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... IO range monitor 3 (C3A46[CS0UBM], C3AC8, and C3ACC) and PCI accesses to this range are claimed by the IC and routed to the ISA bus. If the PNPCS0# function is not selected by PMF6, then this bit has no effect. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet PWRFL_STS Power state power failure ...
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... ENISA. Enable ISA pull-up/down resistors. Read-write. 1=The internal pull-up and pull-down resistors for the ISA bus signals are enabled. This includes pull-ups on IOCHRDY, IOCHK#, IRQ[15,14,11:9,7:3], and SD[7:0]. 0=Disable internal ISA bus resisters. The default state of this bit is latched off the SPKR pin during PWRGD reset. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet ...
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... This field is encoded as follows: SQWAVE Frequency SQWAVE 0h Output low 4h 1h 256 Hz 128 Hz 8192 Hz. 7h Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet ACPI_DIS SIT_DIS RW 4 3:0 Reserved SQWAVE Frequency SQWAVE Frequency 4096 Hz. 8h 256 Hz. ...
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... PITRSM#. Enable the PIT to generate interrupts during POS. 1=Legacy PIT does not generate IRQ0 while in POS, starting from the time that the command to enter POS is sent to PM04. This is necessary to prevent timer-tick interrupts from resuming the system while in POS. 0=PIT generates IRQ0 while in POS. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 28 27:25 TTH_EN ...
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... PMBASE. Read-write. Specifies PCI address bits[15:8] of the 256-byte block of IO-mapped registers used for system management (address space PMxx). Access to this address space is enabled by C3A41[PMIOEN]. PMBLSB. Read only. These bits are fixed in their default state. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet RATIO bits Description 100b 50 ...
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... C3AAC: Audio Port 3 and 4 Trap Address Register Configuration space; function 3; offset: AF-ACh. Default: 0388_0530h. Read-write. 31:16 ADDRAUD4 ADDRAUD3 and ADDRAUD4. Address for the audio trap events 3 and 4. See C3AA8 for details. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 ADDRCA 7:0 MASKCA & (PCI IO space access) & ...
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... C3AC0: PCMCIA Trap Mask Registers Configuration space; function 3; offset: C3-C0h. Default: 0000_0000h. Read-write. 31:24 23:16 MASKPME2 MASKPME1 MASKPME[1,2] and MASKPIO[1,2]. Address mask for the PCMCIA trap events. See C3AB4 for details. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:8 MASKAUD2 15:0 ADDRPIO1 9:0 Reserved 9:0 Reserved ...
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... ADDRMEM1. Memory address for the PMEMRM1 trap event. C3AD4: Programmable Memory Range Monitor 2 Trap Address Register Configuration space; function 3; offset: D7-D4h. Default: 0000_0000h. Read-write. 31:8 ADDRMEM2 ADDRMEM2. Memory address for the PMEMRM2 trap event. See C3AD0 for details. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 ADDRIO1 15:0 ADDRIO3 15:8 MASKIO2 ...
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... This bit resides on the VDD_AUX power plane. WAK_STS. Wakeup status. 1=The system was in a sleep state (S1 to S5) and an enabled resume event occurred. Upon setting this bit, the system resumes. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 MASKMEM1 11 ...
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... STR, S3. Suspend to RAM. 6 STD, S4. Suspend to disk. 7 SOFF, S5. Soft off. SLP_EN. Sleep enable. Write 1 only; reads back as 0. Writing this bit causes the system to sequence into the sleep state specified by SLP_TYP. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 10 RTC_EN 4:1 Reserved 9:3 2 Reserved ...
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... P_LVL3 P_LVL3. Reads from this register initiate the transition of the processor to the C3 state, as specified by C3A50. This register is byte readable only. Reads from this register always return 00h. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 4 NTH_EN NTH_RATIO RATIO bits Description 100b 50 ...
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... IO mapped (base pointer: C3A58); offset: 1Eh. Default: 00h. Read-write. This address accesses the same physical register located at PM2F (i.e., both accesses to PM1E and PM2F identically access the same register and both may be used to set PM28[SWI_STS]). Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet ...
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... THERM_EN. THERM# pin ACPI interrupt enable. RI_EN. RI# pin ACPI interrupt enable. USB_RSM_EN. USB resume event ACPI interrupt enable. Access to this bit is replicated in PM25; there is only one physical register accessed through both PM22 and PM25. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Reserved ...
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... STR, STD, and SOFF. PB_CTL. Power button resume. 1=Enables the assertion of PM00[PWRBTN_STS] to resume the system from STR, STD, and SOFF. PME_CTL. PME# resume. 1=Enables the assertion of PM20[PME_STS] to resume the system from STR, STD, and SOFF. Preliminary Information TM AMD-766 USB_RSM_STS USB_BLK_STS USB_INT_STS USB_ISO_STS USB_CTL_STS 4 ...
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... RI_STS. RI# pin status. Access to this bit is replicated in PM20; see that register. This bit resides on the VDD_AUX power plane. MISC_EVT. Miscellaneous SMI event. Read only. 1=Any of the status bits in PM30 that are enabled in PM32 are active. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Reserved ...
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... IO mapped (base pointer: C3A58); offset: 2Fh. Default: 00h. Read-write. 7:0 SMI_CMD SMI_CMD. SMI command. Writes to this register set PM28[SWI_STS]. Reads of this register provide the data last written to it. Note: This register is identically accessible from offset 1Eh as well (PM1E). Preliminary Information TM AMD-766 THMSMI_EN EXTSMI_EN PMESMI_EN 4 3 ...
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... Reserved TCORLD TCORLD. TCO timer. Reads from this register return the current count of the TCO timer. Writes of any value cause the TCO timer to be reloaded with the value in PM41. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Reserved Reserved Reserved ...
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... BOOT_STS. Boot status. 1=The TCO timer has timed out twice without any BIOS ROM accesses. This is detected when PM46[2NDTO_STS] changes from after any PCIRST# before any BIOS ROM accesses have occurred. This bit resides on the VDD_AUX power plane. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet ...
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... CLKSRC. System inactivity timer clock source. Read-write. Specifies the clock to the system inactivity timer per the following table. CLKSRC Clock period 00b 64 milliseconds 01b 1 second 10b 16 seconds 11b 256 seconds Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Reserved TCOHALT MBL Reserved Reserved Reserved ...
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... Bit[8] AUD_TRP_STS. Audio functions access trap status. Bit[9] VID_TRP_STS. Video functions access trap status. Bit[10] KBM_TRP_STS. Keyboard and mouse access trap status. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Address specification IO space 1F0-1F7h, 3F6h IO space 1F0-1F7h, 3F6h IO space 170-177h, 376h ...
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... Bit[4] FDD_TRP_RLEN. Floppy disk drive access trap causes reload of system inactivity timer. Bit[5] LPT_TRP_RLEN. Parallel port (LPT) access trap causes reload of system inactivity timer. Bit[6] CMA_TRP_RLEN. Serial port A (COM A) access trap causes reload of system inactivity timer. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 80 ...
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... PIC (e.g., bit[12] corresponds to IRQ12). The exception to this is bit[2], which corresponds to the INTR pin, output of the legacy PIC. 1=Enable the corresponding interrupt signal to cause the system inactivity timer to reload when it transitions. 0=Do not affect the system inactivity timer. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:0 IRQRL 81 ...
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... GPIO input path (and may therefore use the polarity, latch, and debounce controls from the GPIO circuit); “Direct” specifies that the signal comes directly from the pad; “NA” specifies that output signal. Preliminary Information TM AMD-766 4 3:2 DEBOUNCE MODE[1:0] Function input path ...
Page 83
... GPIO 0; bit[1] corresponds to GPIO1, and so forth. The latch associated with each GPIO input circuit is cleared when the corresponding bit in this register is written with a 1; writing a 0 has no effect. 31:0 GPIO IRQ status bits Preliminary Information TM AMD-766 MODE Alternate Functions 08h (SMBUSC) 1xb SMBUSC 08h (SMBUSD) ...
Page 84
... SMBus cycle with a 7-bit address that matched the one specified by PMEF. This bit is not set until the end of the acknowledge bit after the last byte is transferred over the SMBus cycle time out Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 15:14 13:7 ...
Page 85
... SMBA_EN. SMBALERT# interrupt enable. Read-write. 1=Enables an SMI or SCI interrupt when PME0[SMBA_STS] is set. 0=No interrupts are generated when this bit is set. This bit has no effect unless the SMBALERT# function is selected by C3A46[10:9]. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Reserved ...
Page 86
... PMEE), then the data targeted to the IC during the cycle is latched in this register. Also, if the address matches the snoop address in PMEF, then the cycle is assumed write word and the data is stored in this register. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 7:1 HSTADDR 0 ...
Page 87
... If there is a match, then PME0[SNP_STS] is set after the cycle completes. If the address specified here matches PMEE, then PME0[SNP_STS] is not set. PM[F5:F4]: General-Purpose IO Pins GPIO[21:20] Select Registers See PMC0 for definitions. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 7:1 HSLVDA 0 SNPLSB 0 ...
Page 88
... Input high voltage IH V Output low voltage OL V Output high voltage OH I Input leakage current LI C Input capacitance IN Note: This table contains preliminary information, which is subject to change. Preliminary Information TM AMD-766 Maximum Comments 3.6 V 3.6 V 5.25 V 3.6 V 3 degrees C 150 degrees C Typical Maximum Comments 3.3 V 3.465 V 3 ...
Page 89
... S8 P6 P10 S10 Y ISA DDATA DDATA DDATA DDATA DDATA BIOS P11 Preliminary Information TM AMD-766 AD2 CBE AD12 AD14 SERR # TRDY # CBE _L0 _L2 AD6 AD8 AD10 AD13 AD15 STOP # IDSEL AD4 AD9 CBE ...
Page 90
... DIOWS# DADDRP2 V18 DRDYP DADDRS0 W18 DRDYS DADDRS1 W17 EKIRQ1 DADDRS2 Y19 EKIRQ12 DCS1P# W19 EXTSMI# Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Ball Signal Name Ball Signal Name V19 FERR# T19 LA21 Y20 FLAGRD# M20 LA22 W20 FLAGWR V8 LA23 ...
Page 91
... SD4 C3 STRAPH1 SD5 B3 STRAPH2 SD6 B4 STRAPL0 SD7 A3 STRAPL1 SERIRQ P17 STRAPL2 SERR# A11 STRAPL3 Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Ball Signal Name Ball Signal Name H17 SUSPEND# M19 VDD_REF G19 TEST# D5 VDD_RTC G20 THERM# U19 VDD_AUX M17 TRDY# ...
Page 92
... Symbol Min Typical A 2.20 2.33 A1 0.50 0.60 A2 0.51 0.56 D 27.00 BSC. D1 24.13 BSC. b 0.60 0.75 e 1.27 BSC. P 24. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet Max Description 2.46 Overall thickness 0.70 Ball height 0.61 Body thickness Body size Ball footprint 0.90 Ball diameter Ball pitch Encapsulation area A20 ...
Page 93
... LA21 4 SD4 14 SD1 5 GPIO19 15 SD0 6 LA23 16 IRQ11 7 SD3 17 LA20 8 GPIO18 18 IOCHRDY 9 LA22 19 GPIO25 10 EKIRQ12 20 IRQ12 Preliminary Information AMD-766 SERR# … NAND Tree Mode 21 LA19 31 CPUSLEEP# 41 LAD1 22 GPIO21 32 KA20G 23 SA16 33 MEMR# 24 IRQ15 34 MEMW# 25 LA18 35 KBRC# 26 GPIO20 36 GPIO9 27 IOW# 37 LAD0 28 IRQ14 38 STRAPL2 ...
Page 94
... PWRBTN# 4 USBN2 14 EXTSMI# 5 USBP1 15 PME# 6 USBN1 16 STRAPH1 7 USBP0 17 STRAPH0 8 USBN0 18 RPWRON 9 INTRUDER# 19 PCIRST# 10 SMBUSC 20 RI# Preliminary Information AMD-766 26 DDATAP3 38 DDRQP 27 SA4 39 DDRQS 28 GPIO27 40 DDATAS6 42 DIOWP# 31 SA3 43 DIOWS# 32 INTIRQ8# 44 DDATAS4 33 DDATAP14 45 DDATAS5 46 DIORP# 35 DDATAP0 47 DIORS# 36 DDATAP15 48 DDATAS3 21 CACHE_ZZ 31 USBOC0# 22 STPCLK# 23 WSC# 24 CPURST# ...
Page 95
... Power Systems, Intel Corporation, Linear Technology Corporation, Maxim Integrated Products, Mitsubishi Electric Corporation, National Semiconductor Corporation, Toshiba Battery Co., Varta Batterie AG, 1996. Universal Serial Bus Specification Revision 1.0. Compaq, DEC, IBM, Intel Corporation, Microsoft, NEC, and Northern Telecom, 1996. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 95 ...
Page 96
... Logical “is not equal to” operator. * Multiply. // This indicates the start of comments. The order in which logical operators are applied is: ~ first, & second, and | last binary or hexadecimal value indicates that the bit(s) may be any value. Preliminary Information TM AMD-766 Peripheral Bus Controller Data Sheet 96 ...