AMD-766 Advanced Micro Devices, AMD-766 Datasheet - Page 10

• Manufacturer Part Number: AMD-766
• Description: Peripheral Bus Controller
• Manufacturer: Advanced Micro Devices

23167B – March 2001
Pin name and description
reset signal from the system keyboard controller. When asserted, an INIT
interrupt to the processor is generated.
LA[23:17]. ISA system address bus bits[23:17]. LA[23:17] and SA[16:0]
combine to for the 24-bit ISA address bus.
LAD[3:0]. LPC address-data bus.
LDRQ0# and LDRQ1#. LPC DMA request signals.
LFRAME#. LPC frame signal.
MEMR#. ISA bus memory cycle read command.
MEMW#. ISA bus memory cycle write command.
OSC. 14.31818 MHz. clock. This is used for the programmable interval
timer and various power management timers.
ROM_KBCS#. ROM chip select and keyboard chip select. This is
designed to be connected to both the ISA-bus system ROM BIOS and the
keyboard controller. During ISA bus memory accesses this pin decodes
ROM BIOS memory space, as defined by C0A43 (if the ISABIOS pin is
high). During ISA bus IO cycles to the legacy keyboard controller, this
pin decodes accesses to the keyboard controller. The state of this bit is
captured during reset in C3A48[3].
SA[16:0]. ISA system address bus bits[16:0]. LA[23:17] and SA[16:0]
combine to for the 24-bit ISA address bus.
SD[7:0]. ISA data bus.
SPKR. Speaker driver from the programmable interval timer. This pin is
an input while PWRGD is low; it is used to select the default state of
C3A48[ENIDE, ENPCI, ENISA] (the internal pull-up-pull-down IO pin
resister enables).
3.5
Pin name and description
DADDR[P,S][2:0]. IDE controller [primary, secondary] port address.
DCS1P#. IDE controller primary port chip select 1. This is active during
accesses to the IO address space 1F7h – 1F0h.
DCS1S#. IDE controller secondary port chip select 1. This is active
during accesses to the IO address space 177h – 170h.
DCS3P#. IDE controller primary port chip select 3. This is active during
accesses to the IO address space 3F7h – 3F4h.
DCS3S#. IDE controller secondary port chip select 3. This is active
during accesses to the IO address space 377h – 374h.
DDACK[P,S]#. IDE controller [primary, secondary] port DMA
acknowledge signal.
DDATA[P,S][15:0]. IO; IDE controller [primary, secondary] port data
bus.
DDRQ[P,S]. Input; IDE controller [primary, secondary] port DMA
request signal.
DIOR[P,S]#. Output; IDE controller [primary, secondary] port IO read
command.
DIOW[P,S]#. Output; IDE controller [primary, secondary] port IO write
command.
DRDY[P,S]. Input; IDE controller [primary, secondary] port ready strobe. Input
Ultra DMA Enhanced IDE Interface
Preliminary Information
AMD-766
TM
IO cell
Output VDD3
Output VDD3
Output VDD3
Output VDD3
IO cell
Output VDD3
Output VDD3
Output VDD3
Output VDD3
Output VDD3
Output VDD3
Output VDD3
Output VDD3
IO-PU VDD3 3-state 3-state 3-state
Input-
Input
Input
type
type
PD
IO
IO
IO
IO
IO
Peripheral Bus Controller Data Sheet
VDD3 3-state 3-state 3-state
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3 3-state 3-state 3-state
VDD3
VDD3
Power
Power
plane
plane
During
During
Reset
Input
Input
Reset
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
-
-
-
-
Reset
Reset
High
High
High
High
High
High
High
High
High
High
High
Post
Low
Low
Low
Post
Low
-
-
-
-
High
High
High
High
High
High
High
High
High
High
High
POS
Last
state
Last
state
Last
state
POS
Low
-
-
-
-
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