CMX969D5 MX-COM, Inc., CMX969D5 Datasheet - Page 12

• Manufacturer Part Number: CMX969D5
• Description: MOTIENT/ARDIS RD-LAP MDC4800 Modem
• Manufacturer: MX-COM, Inc.

MOTIENT
4.5 The Programmer's View
The modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only registers,
individual registers being selected by the A0 and A1 chip inputs: Note that there is a minimum allowable time
between accesses of the modem's registers, see Section 6.1 for details.
4.5.1
This is a 12-byte read/write buffer that is used to transfer data (as opposed to command, status, mode, data
quality or control information) between the modem and the host µC. It appears to the µC as a single 8-bit
register; the modem ensuring that sequential µC reads or writes to the buffer are routed to the correct
locations within the buffer.
The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.
The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive
mode the modem will function correctly even if the µ C does not read the received data from the Data Buffer.
4.5.2
This 8-bit write-only register controls the modem's operating mode (RD-LAP or MDC), symbol rate and the
response times of the receive clock extraction and signal level measurement circuits.
4.5.2.1
These bits control a frequency divider driven from the clock signal present at the XTAL pin, and hence
determine the nominal symbol and bit rates. The following table shows the settings of B7 and B6 needed for
19200bps RD-LAP and 4800bps MDC4800 operation.
Note: The setting B7 = 1 and B6 = 1 cannot be used with 19200bps RD-LAP / 4800bps MDC4800 as this
would require a Xtal frequency above the oscillator operating range.
The CMX969 may also be used with a 9600bps RD-LAP system if the Xtal frequency is 4.9152 or 7.3728MHz
and Control register bits 7-6 set to ‘1 0’ or ‘1 1’
4.5.2.2
This bit should always be set to ‘0’.
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4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
B7
0
0
1
1
SM
Data Block Buffer
Control Register
/ARDIS
Control Register B7, B6: CKDIV - Clock Division Ratio
Control Register B5: Reserved for future use.
B6
0
1
0
1
SM
RD-LAP
A1
0
0
1
1
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TM
Xtal Frequency
MDC4800 Modem
4.9152 MHz
7.3728 MHz
9.8304 MHz
Control Register
A0
See note
0
1
0
1
7
CKDIV
6
Command Register
Write to Modem
Control Register
Mode Register
Reserved,
set to '0'
Data Buffer
5
ALTCRC
4
RD-LAP Symbol Rate
ALTFILT
12
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Xtal frequency /
3
1024
1536
512
768
MDC
Reserved for other uses.
2
Data Quality Register
Read from Modem
FSTOL
Status Register
Data Buffer
Division ratio:
1
HOLD
0
MDC4800 Symbol Rate
Xtal frequency /
CMX969 Advance Information
1024
1536
2048
3072
Doc. # 20480211.002