CMX969D5 MX-COM, Inc., CMX969D5 Datasheet - Page 14

• Manufacturer Part Number: CMX969D5
• Description: MOTIENT/ARDIS RD-LAP MDC4800 Modem
• Manufacturer: MX-COM, Inc.

MOTIENT
4.5.3.4
Setting this bit to ‘1’ removes power from all of the CMX969’s circuitry, including the Xtal oscillator, the V
supply and the Tx output buffer. The µC interface will continue to operate except for the Command Register
which will not recognize or execute commands when ZP is ‘1’ as it relies on a clock source for correct
operation.
To obtain the lowest power consumption in Zero-Power mode, the Mode Register
set to 0 when the ZP bit (B4) is set to ‘1’.
4.5.3.5
When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx Symbol and
Clock extraction circuits and the Tx output buffer will be disabled, and the TXOUT pin will be connected to
V
will continue to operate.
Setting the PSAVE bit to '0' when the ZP bit is ‘0’ restores power to all of the chip circuitry. Note that the
internal filters - and hence the TXOUT pin in transmit mode - will take about 20 symbol-times to settle after
the PSAVE bit is taken from '1' to '0'.
4.5.3.6
In receive mode, setting this bit to '1' causes the IRQ bit of the status register to be set to '1' whenever a new
channel status 'S' symbol has been received. (The SRDY bit of the Status Register will also be set to '1' at the
same time, and the SVAL bits updated to reflect the received 'S' symbol.)
In transmit mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a 'S'
symbol or channel status bit has been transmitted. (The SRDY bit of the Status Register will also be set to '1'
at the same time.)
In MDC mode, no interrupt is generated for the unused ‘94
4.5.3.7
In transmit mode these two bits define the next 'S' symbol or channel status bit to be transmitted. These bits
have no effect in receive mode.
4.5.4
Writing to this register tells the modem to perform a specific action or actions, depending on the setting of the
AFSD and TASK bits, and controls the RxEye function.
Note: The Command Register uses internal clocks derived from the XTAL input to decode and carry out any
task written to it. To allow time for the Xtal oscillator to start up, it is advisable to postpone writing to the
Command Register until about 20ms after power is applied to the CMX969 or the Mode Register ZP bit is
changed from ‘1’ to ‘0’.
When it has no action to perform, the modem will be in an 'idle' state. If the modem is in transmit mode the
input to the Tx filter will be connected to V
received data quality and extract symbols from the received signal, supplying them to the de-interleave buffer,
but will otherwise ignore the received data.
¤ ¤ ¤ ¤ 2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
BIAS
through a high value resistance. The Xtal Clock oscillator, Rx input amplifier and the µC interface logic
SM
Command Register
/ARDIS
Mode Register B4: ZP - Zero Power
Mode Register B3: PSAVE - Powersave
Mode Register B2: SSIEN - 'S' Symbol IRQ Enable
Mode Register B1, 0: SSYM - 'S' Symbol To Be Transmitted
SM
RD-LAP
www.mxcom.com Tel: [phone] 744 5050 Fax: [phone]
TM
MDC4800 Modem
Command Register
AFSD
7
B1
RXEYE
1
1
0
0
6
BIAS
5
. In receive mode the modem will continue to measure the
B0
1
0
0
1
Reserved,
set to '0'
4
14
All trademarks and service marks are held by their respective companies.
RD-LAP
3
th
‘+3’
‘+1’
‘-1’
‘-3’
bit’ in each block.
2
TASK
1
MDC
‘+1’
‘+1’
‘-1’
‘-1’
0
TX/
CMX969 Advance Information
RX
bit (B5) should be
Doc. # 20480211.002
BIAS