ACS8526 Semtech Corporation, ACS8526 Datasheet - Page 12

• Manufacturer Part Number: ACS8526
• Description: Lc/p Lite Line Card Protection Switch For Pdh, Sonet, or SDH Systems
• Manufacturer: Semtech Corporation

Figure 4 PLL Block Diagram
DFS is a technique for generating an output frequency
using a higher frequency system clock (204.8 MHz in the
case of the 77.76 MHz synthesis). However, the edges of
the output clock are not ideally placed in time, since all
edges of the output clock will be aligned to the active edge
of the system clock. This means that the generated clock
will inherently have jitter on it equivalent to one period of
the system clock.
DPLL1 and APLLs
DPLL1 always produces 77.76 MHz. The input reference
is either passed directly to the PFD or via a pre-divider (not
shown) to produce the reference input. The feedback
77.76 MHz is either divided or synthesized to generate
the locking frequency.
The DPLL1 77M Forward DFS block uses DFS clocked by
the 204.8 MHz system clock to synthesize the 77.76 MHz
and, therefore, has an inherent 4.9 ns of pk-pk jitter.
There is an option to use a feedback APLL (APLL3) to filter
out this jitter before the 77.76 MHz is used to generate
the feedback locking frequency in the DPLL1 feedback
DFS block. This analog feedback option allows a lower
jitter (<1 ns) feedback signal to give maximum
performance.
Revision 4.00/September 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
DPLL1
Reference
Input
DPLL1
DPLL2
sts_current_phase
Loop Filter
PFD and
Locking
Frequency
Loop Filter
sts_current_phase
PFD and
8 kHz
8 kHz
Feedback
Forward
77M
DFS
DFS
DPLL2_frequency
Feedback
Forward
DFS
DFS
1
0
0
1
DPLL2_dig_
feedback
DPLL1_frequency
FINAL
Output
0
1
Page 12
DFS
LF
The 77.76 MHz is fed to DPLL1 LF Output DFS block and
to APLL1. The low frequency DPLL1 LF Output DFS block
is used to produce three frequencies; two of them,
Digital1 and Digital2, are available for selection to be
produced at outputs O1 and O2, and the third frequency
can produce multiple E1/DS1 rates via the filtering APLLs.
The input clock to the DPLL1 LF Output DFS block is
77.76 MHz from APLL1 (post jitter filtering) or 77.76 MHz
direct from the DPLL1 77M Forward DFS.
Utilizing the clock from APLL1 will result in lower jitter
outputs from the DPLL1 LF Output DFS block. However,
when the input to the APLL1 is taken from the DPLL1 LF
Output DFS block, the input to that block comes directly
from the DPLL1 77M Forward DFS block so that a “loop”
is not created.
APLL1 is for multiplying and filtering. The input to APLL1 is
controlled by MUX 1 (see “Multiplexers” on page 13). The
frequency from APLL1 is four times its input frequency i.e.
311.04 MHz when used with a 77.76 MHz input. APLL1 is
subsequently divided by 1, 2, 4, 6, 8, 12, 16 and 48 and
these are available at the O1 and O2 Outputs.
DPLL2 & APLLs
DPLL2 is simpler than DPLL1. DPLL2 offers no low
frequency output. The DPLL2 input can only be used to
DPLL1_freq_to_APLL2
DPLL1_frequency
0
1
0
1
MUX
MUX X
2
1
ACS8526 LC/P LITE
APLL2
APLL1
APLL3
Dividers
Dividers
Output
Output
APLL2
APLL1
Analog
F8526D_017BLOCKDIA_01
DATASHEET
www.semtech.com
01 and 02
01 and 02
FrSync
MFrSync
O1 and O2