ACS8526 Semtech Corporation, ACS8526 Datasheet - Page 33

• Manufacturer Part Number: ACS8526
• Description: Lc/p Lite Line Card Protection Switch For Pdh, Sonet, or SDH Systems
• Manufacturer: Semtech Corporation

Address (hex):
Revision 4.00/September 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
phase_alarm
Bit No.
Bit 7
7
6
5
4
3
2
1
0
03
test_register1
disable_180
Description
phase_alarm (phase alarm (R/O))
Instantaneous result from DPLL1.
disable_180
Normally the DPLL will try to lock to the nearest
edge (±180°) for the first 2 seconds when locking to
a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ±360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to two
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
Not used.
resync_analog (analog dividers re-synchronization)
The analog output dividers include a
synchronization mechanism to ensure phase lock at
low frequencies between the input and the output.
Set to 0
Test Control. Leave unchanged or set to 0.
8k Edge Polarity
When Lock8k or DivN mode is selected for the
current input SEC, this bit allows the system to lock
on either the rising or the falling edge of the input
clock.
Set to 0
Test Control. Leave unchanged or set to 0.
Set to 0
Test Control. Leave unchanged or set to 0.
Bit 6
Bit 5
Description
resync_analog
Bit 4
FINAL
Page 33
(R/W) Register containing various
test controls (not normally used).
Set to 0
Bit Value
Bit 3
0
1
0
1
0
1
0
0
1
0
0
-
8k Edge Polarity Set to 0
Value Description
DPLL1 reporting phase locked.
DPLL1 reporting phase lost.
DPLL1 automatically determines frequency lock
enable.
DPLL1 forced to always frequency and phase lock.
-
Analog divider only synchronized during first 2
seconds after power-up.
Analog dividers always synchronized.This keeps the
clocks divided down from the APLL output, in sync
with equivalent frequency digital clocks in the DPLL.
Hence ensuring that 6.48 MHz output clocks, and
above, are in sync with the DPLL even though only a
77.76 MHz clock drives the APLL.
-
Lock to falling clock edge.
Lock to rising clock edge.
-
-
Bit 2
ACS8526 LC/P LITE
Default Value
Bit 1
DATASHEET
www.semtech.com
00X1 0100
Set to 0
Bit 0