AD9851 Analog Devices, AD9851 Datasheet - Page 11

• Manufacturer Part Number: AD9851
• Description: CMOS 180 MHz DDS/DAC Synthesizer
• Manufacturer: Analog Devices

Results of Reset, Figure 14
– Phase Accumulator zeroed such that the output = 0 Hertz
– Phase Offset register set to zero such that DAC IOUT = Full-
– Internal Programming Address pointer reset to W0.
– Power-down bit reset to “0” (power-down disabled).
– 40-bit Data Input Register is NOT cleared.
– 6 Reference Clock multiplier is disabled.
– Parallel programming mode selected by default.
Figure 15. Parallel-Load Power-Down Sequence/Internal
Operation
Figure 16. Parallel-Load Power-Up Sequence (to Recover
from Power-Down)/Internal Operation
REV. C
DATA (W0)
DATA (W0)
(dc).
Scale output and IOUTB = zero mA output.
STROBE
SYSCLK
SYSCLK
W CLK
FQ UD
W CLK
FQ UD
DAC
INTERNAL CLOCKS
XXXXX00X
XXXXX10X
ENABLED
SYSCLK
RESET
A
OUT
SYMBOL
t
t
t
t
t
*
RH
RL
RR
RS
OL
SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
Figure 14. Master Reset Timing Sequence
t
RH
INTERNAL CLOCKS
DISABLED
CLK DELAY AFTER RESET RISING EDGE 3.5ns*
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
RESET OUTPUT LATENCY
DEFINITION
t
RS
–11–
t
OL
Entry to the serial mode, Figure 17, is via the parallel mode
which is selected by default after a RESET is asserted. One
needs only to program the first eight bits (word W0) with the
sequence xxxxx011 as shown in Figure 17 to change from paral-
lel to serial mode. The W0 programming word may be sent over
the 8-bit data bus or hardwired as shown in Figure 18. After
serial mode is achieved, the user must follow the programming
sequence of Figure 19.
Note: After serial mode is invoked, it is best to immediately
write a valid 40-bit serial word (see Figure 19), even if it is all
zeros, followed by a FQ_UD rising edge to flush the “residual”
data left in the DDS core. A valid 40-bit serial word is any word
where W33 is Logic 0.
Figure 18. Hardwired xxxxx011 Configuration for Serial-
Load Enable Word W0 in Figure 17
DATA (W0)
W CLK
FQ UD
Figure 17. Serial-Load Enable Sequence
t
RL
SUPPLY
t
RR
3.5ns*
5 SYSCLK CYCLES
13 SYSCLK CYCLES
2 SYSCLK CYCLES
+V
MIN SPEC
10k
COS (0 )
XXXXX011
1
2
3
4
D3
D2
D1
D0
AD9851
ENABLE
SERIAL MODE
AD9851
D4
D5
D6
D7
28
27
26
25