CY37032VP Cypress Semiconductor Corp., CY37032VP Datasheet - Page 15

• Manufacturer Part Number: CY37032VP
• Description: 5V, 3.3V, Isr High-performance CPLDS
• Manufacturer: Cypress Semiconductor Corp.

5.0V Device Electrical Characteristics
Inductance
Capacitance
Endurance Characteristics
Document #: 38-03007 Rev. **
V
V
V
V
V
I
I
I
I
I
I
I
L
C
C
C
N
Notes:
Parameter
IX
OZ
OS
BHL
BHH
BHLO
BHHO
Parameter
4.
5.
6.
7.
8.
9.
OH
OHZ
OL
IH
IL
I/O
CLK
DP
Parameter
I
Tested initially and after any design or process changes that may affect these parameters.
When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
problems caused by tester ground degradation.
Dual pins are I/O with JTAG pins.
OH
Parameter
= –2 mA, I
[5]
Output HIGH Voltage
Output HIGH Voltage with
Output Disabled
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit
Current
Input Bus-Hold LOW
Sustaining Current
Input Bus-Hold HIGH
Sustaining Current
Input Bus-Hold LOW Overdrive
Current
Input Bus-Hold HIGH Overdrive
Current
Maximum Pin
Inductance
[5]
OL
Description
Minimum Reprogramming Cycles
= 2 mA for TDO.
[8, 5]
Description
Input/Output Capacitance
Clock Signal Capacitance
Dual Function Pins
Description
[5]
V
at f = 1 MHz
Conditions
IN
Description
[5]
= 5.0V
Test
[9]
TQFP
V
V
V
Guaranteed Input Logical HIGH Voltage
for all Inputs
Guaranteed Input Logical LOW Voltage
for all Inputs
V
V
Bus-Hold Disabled
V
V
V
V
V
Lead
44-
Over the Operating Range
CC
CC
CC
I
O
CC
CC
CC
CC
CC
2
= GND OR V
= GND or V
= Min. I
= Max. I
= Min. I
= Max., V
= Min., V
= Min., V
= Max.
= Max.
Normal Programming Conditions
PLCC
V
V
V
Lead
44-
IN
IN
IN
5
Test Conditions
[7]
[7]
= 5.0V at f = 1 MHz at T
= 5.0V at f = 1 MHz at T
= 5.0V at f = 1 MHz at T
I
I
I
I
I
IL
IH
OH
OH
OH
OH
OH
OH
OL
OL
OUT
CC
CC
= 0.8V
= 2.0V
Test Conditions
= –3.2 mA (Com’l/Ind)
= 16 mA (Com’l/Ind)
= 12 mA (Mil)
= –2.0 mA (Mil)
= 0 A (Com’l)
= 0 A (Ind/Mil)
= –100 A (Com’l)
= –150 A (Ind/Mil)
, Output Disabled,
CLCC
, Bus-Hold Disabled
Lead
= 0.5V
Test Conditions
44-
2
PLCC
Lead
84-
8
[4]
[6]
[4]
[6]
Ultra37000™ CPLD Family
[6]
CLCC
[6]
A
A
A
Lead
[4]
84-
= 25 C
= 25 C
= 25 C
[4]
5
[2]
Min.
–0.5
OUT
–10
–50
–30
+75
–75
2.4
2.4
2.0
TQFP
Lead
100-
= 0.5V has been chosen to avoid test
8
1,000
Min.
Max.
Typ.
10
12
16
TQFP
Lead
160-
9
10,000
Typ.
V
+500
Max.
–160
–500
CCmax
4.2
4.5
3.6
3.6
0.5
0.5
0.8
10
50
PQFP
Lead
Page 15 of 67
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11
Unit
Cycles
pF
pF
pF
Unit
Unit
mA
Unit
V
V
V
V
V
V
V
V
V
V
nH
A
A
A
A
A
A