CY37032VP Cypress Semiconductor Corp., CY37032VP Datasheet - Page 7

• Manufacturer Part Number: CY37032VP
• Description: 5V, 3.3V, Isr High-performance CPLDS
• Manufacturer: Cypress Semiconductor Corp.

Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchro-
nous product term clock PTCLK. Each input macrocell has
access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial, reg-
istered, double-registered, or latched. In addition, these pins
feed the clocking structures throughout the device. The clock
path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000 fam-
ily also has a product term clock for asynchronous clocking.
Each logic block has an independent product term clock which
is available to all 16 macrocells. Each product term clock also
supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and sys-
tem performance is unaffected by the features used. Figure 5
illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input set-
up time to the output macrocells for any input is 3.5 ns and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
Document #: 38-03007 Rev. **
POLARITY INPUT
FROM CLOCK
CLOCK PINS
INPUT/CLOCK PIN
0
1
2
3
C8 C9
O
D
D
LE
Q
Q
Figure 4. Input/Clock Macrocell
D
Q
The Ultra37000 features:
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable tim-
ing model ensures compliance with the PCI AC specifications
independent of the design.
INPUT
INPUT
CLOCK
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
0
1
C12
0
1
2
3
C10C11
O
t
S
= 3.5 ns
Figure 5. Timing Model for CY37128
O
TO PIM
Ultra37000™ CPLD Family
COMBINATORIAL SIGNAL
REGISTERED SIGNAL
TO CLOCK MUX ON
ALL INPUT MACROCELLS
t
PD
C13, C14, C15
D,T,L
= 6.5 ns
O
0
1
O
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
OR C16
t
CO
= 4.5 ns
Page 7 of 67
TO CLOCK MUX
IN EACH
LOGIC BLOCK
OUTPUT
OUTPUT