XR16L788 Exar Corporation, XR16L788 Datasheet - Page 13

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

XR16L788 OCTAL UART
REV. 1.1.4
.
There are 8 UARTs [channel 7:0] in the 788. Each
has its own 64-byte of transmit and receive FIFO, a
set of 16550 compatible control and status registers,
and a baud rate generator for individual channel data
rate setting. Eight additional registers per UART were
added for the EXAR enhanced features.
Each UART has its own Baud Rate Generator (BRG)
with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR
4.0 UART
4.1 P
ROGRAMMABLE
T
ABLE
5: T
C H 0 0 x0 0 R e a d R H R
C H 2 0 x2 0 R e a d R H R
C H 3 0 x3 0 W rite T H R
C H 3 0 x3 0 R e a d R H R
C H 4 0 x4 0 R e a d R H R
C H 0 0 x0 0 W rite T H R
C H 1 0 x1 0 W rite T H R
C H 1 0 x1 0 R e a d R H R
C H 2 0 x2 0 W rite T H R
C H 4 0 x4 0 W rite T H R
C H 5 0 x5 0 W rite T H R
C H 5 0 x5 0 R e a d R H R
C H 7 0 x7 0 R e a d R H R
C H 6 0 x6 0 R e a d R H R
C H 6 0 x6 0 W rite T H R
C H 7 0 x7 0 W rite T H R
RANSMIT AND
B
TH R and R H R A dd ress Locations F or C H0 to C H 7 (16C 550 Co m patib le)
AUD
R
ATE
R
G
ECEIVE
ENERATOR
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
D
ATA
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
R
EGISTER
13
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
register. The MCR register bit-7 sets the prescaler to
divide the input crystal or external clock by 1 or 4. The
output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor
between 1 and (2
pling clock of the serial data rate. The sampling clock
is used by the transmitter for data bit shifting and re-
ceiver for data sampling. The BRG divisor (DLL and
DLM registers) defaults to a random value upon pow-
er up. Therefore, the BRG must be programmed dur-
ing initialization to the operating data rate.
, 16C550
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
COMPATIBLE
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
16
-1) to obtain a 16X or 8X sam-
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
TH R R H R 1
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0