MAX3890ECB Maxim, MAX3890ECB Datasheet - Page 8

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MAX3890ECB

Manufacturer Part Number
MAX3890ECB
Description
+3.3V / 2.5Gbps / SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
Manufacturer
Maxim
Datasheet

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Figure 4 shows alternative PECL-output termination
methods. Use Thevenin-equivalent termination when a
(V
coupling is necessary, be sure that the coupling capac-
itor is placed following the 50
DC termination.
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3890 clock and data inputs and
outputs.
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
Figure 3. Current-Mode Logic
8
CC
_______________________________________________________________________________________
- 2V) termination voltage is not available. If AC-
Alternative PECL-Output Termination
Applications Information
50
V
GND
CC
Layout Techniques
OUTPUT CIRCUIT
or Thevenin-equivalent
50
STRUCTURE
ESD
SLBO+
SLBO-
Figure 4. Alternative PECL-Output Termination
MAX3890
MAX3890
OR SDO+
OR SDO+
OR SDO-
OR SDO-
SCLKO+
SCLKO+
SCLKO-
SCLKO-
V
SLBI+
SLBI-
CC
50
V
CC
Z
Z
Z
Z
+3.3V
0
0
0
0
INPUT CIRCUIT
- 2V
= 50
= 50
= 50
= 50
130
50
50
82
130
50
82
HIGH-
IMPEDANCE
INPUTS
PECL
INPUTS

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