MAX536 Maxim, MAX536 Datasheet - Page 15

• Manufacturer Part Number: MAX536
• Description: Calibrated / Quad / 12-Bit Voltage-Output DACs with Serial Interface
• Manufacturer: Maxim

of the MAX536/MAX537 can be shifted out of SDO and
returned to the microprocessor for data verification; data
in the MAX536/MAX537 input/DAC registers cannot be
read.)
With a 3-wire interface (CS, SCK, SDI) and LDAC tied
high, the DACs are double-buffered. In this mode,
depending on the command issued through the serial
interface, the input register(s) may be loaded
without affecting the DAC register(s), the DAC register(s)
can be loaded directly, or all four DAC registers may be
simultaneously updated from the input registers. With a 3-
wire interface (CS, SCK, SDI) and LDAC tied low (Figure
4), the DAC registers remain transparent. Any time an
input register is updated, the change appears at the DAC
output with the rising edge of CS.
The 4-wire interface (CS, SCK, SDI, LDAC) is similar to
the 3-wire interface with LDAC tied high, except LDAC is
a hardware input that simultaneously and asynchronously
loads all DAC registers from their respective input regis-
ters when driven low (Figure 5).
The MAX536/MAX537 require 16 bits of serial data. Data is
sent MSB first and can be sent in two 8-bit packets or one
16-bit word (CS must remain low until 16 bits are trans-
ferred). The serial data is composed of two DAC address
bits (A1, A0), two control bits (C1, C0), and the 12 data bits
D11…D0 (Figure 7). The 4-bit address/control code deter-
mines the following: 1) the register(s) to be updated and/or
the status of the input and DAC registers (i.e., whether they
are in transparent or latch mode), and 2) the edge on which
data is clocked out of SDO.
Figure 6 shows the serial-interface timing requirements. The
chip-select pin (CS) must be low to enable the DAC’s serial
interface. When CS is high, the interface control circuitry is
disabled and the serial data output pin (SDO) is driven high
(MAX537) or is a high-impedance open drain (MAX536). CS
must go low at least t
edge to properly clock in the first bit. When CS is low, data is
Figure 7. Serial-Data Format (MSB Sent First)
MSB ..................................................................................LSB
Address
A1
Bits
Control Bits
4 Address/
A0
C1
Control
Voltage-Output DACs with Serial Interface
Bits
C0
______________________________________________________________________________________
16 Bits of Serial Data
CSS
MSB.............................................LSB
D11................................................D0
Serial-Interface Description
before the rising serial clock (SCK)
12 Data Bits
Data Bits
Calibrated, Quad, 12-Bit
clocked into the internal shift register via the serial data input
pin (SDI) on SCK’s rising edge. The maximum guaranteed
clock frequency is 10MHz. Data is latched into the appropri-
ate MAX536/MAX537 input/DAC registers on CS’s rising
edge.
Interface timing is optimized when serial data is clocked out
of the microcontroller/microprocessor on one clock edge
and clocked into the MAX536/MAX537 on the other edge.
Table 1 lists the serial-interface programming commands.
For certain commands, the 12 data bits are “don’t cares”.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simultane-
ously loaded with the same digital code from the input shift
register. The NOP (no operation) command allows the regis-
ter contents to be unaffected and is useful when the
MAX536/MAX537 are configured in a daisy-chain (see the
Daisy-Chaining Devices section). The command to change
the clock edge on which serial data is shifted out of the
MAX536/MAX537 SDO pin also loads data from all input reg-
isters to their respective DAC registers.
The serial-data output, SDO, is the internal shift register’s
output. The MAX536/MAX537 can be programmed so that
data is clocked out of SDO on SCK’s rising (Mode 1) or
falling (Mode 0) edge . In Mode 0, output data at SDO lags
input data at SDI by 16.5 clock cycles, maintaining compati-
bility with Microwire, SPI/QSPI, and other serial interfaces. In
Mode 1, output data lags input data by 16 clock cycles. On
power-up, SDO defaults to Mode 1 timing.
For the MAX536, SDO is an open-drain output that should be
pulled up to +5V. The data sheet timing specifications for
SDO use a 1k pull-up resistor. For the MAX537, SDO is a
complementary output and does not require an external
pull-up.
The test pin (TP) is used for pre-production analysis of the IC.
Connect TP to V
Failure to do so affects DAC operation.
Any number of MAX536/MAX537s can be daisy-chained by
connecting the SDO pin of one device (with a pull-up resis-
tor, if appropriate) to the SDI pin of the following device in the
chain (Figure 8).
Since the MAX537’s SDO pin has an internal active pull-up,
the SDO sink/source capability determines the time required
to discharge/charge a capacitive load. Refer to the serial
data out V
Characteristics.
OH
and V
DD
for proper MAX536/MAX537 operation.
OL
specifications in the Electrical
Daisy-Chaining Devices
Serial-Data Output
Test Pin
15