MAX536 Maxim, MAX536 Datasheet - Page 18

• Manufacturer Part Number: MAX536
• Description: Calibrated / Quad / 12-Bit Voltage-Output DACs with Serial Interface
• Manufacturer: Maxim

Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
PORT D of the 68HC11 supports SPI. The four registers
used for SPI operation are the Serial Peripheral Control
Register, the Serial Peripheral Status Register, the Serial
Peripheral Data I/O Register, and PORT D’s Data Direction
Register. These registers have a default starting location of
$1000.
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose
inputs. Setting bit 6 (SPE) of the Serial Peripheral Control
Register (SPCR) configures PORT D for SPI as follows:
Table 2. Serial Peripheral Control-Register Definitions
Table 3. Serial Peripheral Status-Register Definitions
18
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
__________Applications Information
SPR1/0
DWOM
NAME
CPHA
MSTR
CPOL
NAME
WCOL
MODF
BIT
7
NAME
–
SPIE
SPE
SPIF
______________________________________________________________________________________
6
–
Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to
determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral
Status Register’s SPIF bit or MODF bit is set.
Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a general-
purpose I/O port.
When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
Master/Slave select option
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
clock idles low.
Determines the clock phase.
SPI Clock-Rate Select
SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR.
The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by read-
ing the SPSR and then accessing the SPDR.
The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.
SS
SPR1
5
0
0
1
1
SCK MOSI MISO TXD
Interfacing to the M68HC11*
4
SPR0
0
1
0
1
3
µP clock divided by 2
µP clock divided by 4
µP clock divided by 16
µP clock divided by 32
2
1
RXD
0
DEFINITION
DEFINITION
Bits 6 and 7 are not used. Writes to these bits are ignored.
The PORT D Data Direction Register (DDRD) deter-
mines whether the port bits are inputs or outputs. Its
configuration is shown below:
Setting DDD_ = 0 configures the port bit as an input, while
setting DDD_ = 1 configures the port bit as an output. Writes
to bits 6 and 7 have no effect.
In SPI mode with MSTR = 1, when a PORT D bit is expected
to be an input (SS, MISO, RXD), the corresponding DDRD bit
(DDD_) is ignored. If the bit is expected to be an output
(SCK, MOSI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.
BIT
7
NAME
–
6
–
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
5
4
3
2
1
0