MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 24

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

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2.3.2
Extended Direct Accessing employs the high and low address registers to perform page addressing. The address
within the page is provided directly by the CPU address bus. Similarly, the data is fetched/placed directly on the
CPU data bus.
The access address is written to registers 008h and 00Ah. This will perform only the page addressing. Upon
assertion of the address within the page, the MT92220 will read/write the data with respect to that address. The
cpu_a_das pin is set when the data read/write occurs. When operating the CPU interface in direct mode with a
16-bit data bus, extended_a[19:16], are employed for the lower address word register 00Ah. However, when
operating the CPU interface in direct mode with an 8-bit data bus, bits [19:15] are used for the lower address word.
2.3.2.1 Extended Direct Writes
1. Write the upper address, extended_a[32:20], to register 008h. This may not be required if previous value holds
2. Write the lower address, extended_a [19:16] or [19:15] to register 00Ah. The remaining bits [15:4] or [14:4] are
3. Write write_enable[13:12] (This may not be required if previous value holds true) and extended_parity[15:14].
4. Write data value to the address within the corresponding memory page with the cpu_a_das pin set.
2.3.2.2 Extended direct reads
1. Write the upper address, extended_a[32:20], to register 008h. This may not be required if previous value holds
2. Write the lower address, extended_a [19:16] or [19:15] to register 00Ah. The remaining bits [15:4] or [14:4] are
3. Assert the lower address within the memory page and fetch the read data with cpu_a_das set.
4. Read the extended_parity field (optional), extended_parity[15:14], register 000h.
2.4
The reset procedure for the MT92220 requires several steps, mostly due to the fact that there are several levels of
hardware and software resets in the chip. All register accesses in the reset procedure maybe performed in either
Direct or Indirect mode. The procedure to configure the chip is as follows:
1. Assert the nreset pin for at least one 1 ms.
2. De-assert the nreset pin.
3. Clear nreset bit in Register 100h, set Bit 9 (mem_oe), Bit 10 (ethernet_enable, if necessary), Bit 13
4. Configure upclk frequency in Register 10Ah.
5. Configure the fast_clock PLLs in Register 110h, 170h, 172h.
6. Configure H.110 PLL in Register 174h.
7. Set proper divisors in Register 164h, 166h.
8. Reset Bit 9 (mem_oe) in Register 100h.
9. Set Bit 0 (nreset_registers) in CPU Register 100h.
10. Set active levels for interrupt pins in the Main Registers (214h, 216h).
11. Configure external memories in the Main Registers (230h, 232h, 234h, 236h, 240h).
12. Set Bit 1 (nreset_chip) in CPU Register 100h.
13. Configure all the other registers.
14. Set Bit 2 (nreset_network) in CPU Register 100h.
true.
ignored. This may not be required if previous value holds true.
The extended parity write is optional.
true.
ignored. This may not be required if previous value holds true.
(low_latency_cpu_accesses) in Register 100h.
Extended Direct Access Procedures
MT92220 Reset Procedure
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