MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 46

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

46
Once written in the Packet Assembly Control & Data FIFOs, the packets are read out by one of two processes
depending on their nature: AAL2 packets are read by the TX AAL2 VC process. This process associates the packet
to a TX AAL2 VC Structure and assembled AAL2 cells with these packets. Any complete AAL2 cells are then
written to their eventual destination: the destination is contained in the TX AAL2 VC structure. The payload of the
cells is written into the Raw Cell Buffer, while the Raw Cell Pointers are written into one of the 6 TX Link Raw Cell
Buffer Pointers, the RX CPU Raw Cell Buffer Pointers (for internal diagnostic), or the RX AAL2 Raw Cell Buffer
Pointers (for internal loopback).
RTP packets will be read by the Assembly Copying Process that then writes the packets into their destination
buffer. The payload of RTP packets is written into the Network Packet Buffer, while the handle to the packet is
written into one of 6 destinations: one of the 4 TX Link Packet Buffer Handles, the Network CPU Packet Buffer
Handles (for internal diagnostic), or the Packet Identifier Buffer Handles (for internal loopback).
HDLC Packet Treatment Process: When an HDLC packet completes, this process will generate an event pointing to the correct TX AAL2
HDLC Packet Treatment Process: When an HDLC packet completes, this process will generate an event pointing to the correct TX AAL2
Connection Structure or TX RTP Connection Structure, indicating that a packet should be sent to the network.
Connection Structure or TX RTP Connection Structure, indicating that a packet should be sent to the network.
Service Indicator Process: Schedules the Assembly of RTP and AAL2 xxPCM packets. The service timer reads the Service Indicator Tables
Service Indicator Process: Schedules the Assembly of RTP and AAL2 xxPCM packets. The service timer reads the Service Indicator Tables
synchronously with the H.110 bus and generates assembly events when enough payload is present to assemble a complete packet.
synchronously with the H.110 bus and generates assembly events when enough payload is present to assemble a complete packet.
Packet Assembly: Based on assembly events, generates RTP and AAL2 packets and all the appropriate headers as well. Also performs silence
Packet Assembly: Based on assembly events, generates RTP and AAL2 packets and all the appropriate headers as well. Also performs silence
suppression on xxPCM data.
suppression on xxPCM data.
CPU RTP-AAL2 packet injection: Software process that copies packets to be sent into SSRAM, then injects a send event into the Event Queue.
CPU RTP-AAL2 packet injection: Software process that copies packets to be sent into SSRAM, then injects a send event into the Event Queue.
Event indicating HDLC
Event indicating HDLC
packet complete
packet complete
Circular Buffer
Circular Buffer
Circular Buffer
Circular Buffer
Circular Buffer
Circular Buffer
Packets (CPU-
Packets (CPU-
(1 per Stream)
(1 per Stream)
(1 per Stream)
(1 per Bearer)
(1 per Bearer)
(1 per Bearer)
TX xxPCM
TX xxPCM
TX xxPCM
managed)
managed)
TX HDLC
TX HDLC
TX HDLC
TXCIRC5
TXCIRC5
TXCIRC5
TXCIRC4
TXCIRC4
TXCIRC4
AAL2 packet
AAL2 packet
TX CPU
TX CPU
CPU RTP-
CPU RTP-
injection
injection
entry per stream)
entry per stream)
entry per stream)
HDLC Stream to
HDLC Stream to
HDLC Stream to
LUT Structure (1
LUT Structure (1
LUT Structure (1
HDLC Address
HDLC Address
HDLC Address
TXTDM4
TXTDM4
TXTDM4
Table) SERVTIM1
Table) SERVTIM1
Table) SERVTIM1
Service Indicator
Service Indicator
Service Indicator
Control Memory
Control Memory
Control Memory
(1 entry per
(1 entry per
(1 entry per
Indicator
Indicator
Indicator
Process
Process
Process
Service
Service
Service
channel) TXTDM6
channel) TXTDM6
channel) TXTDM6
entry per HDLC
entry per HDLC
entry per HDLC
HDLC Address
HDLC Address
HDLC Address
HDLC Packet
HDLC Packet
HDLC Packet
LUT (AAL2) (1
LUT (AAL2) (1
LUT (AAL2) (1
Treatment
Treatment
Treatment
Process
Process
Process
Zarlink Semiconductor Inc.
Figure 21 - Tx Flow 2
Assembly Event
Assembly Event
Assembly Event
channel) TXTDM5
channel) TXTDM5
channel) TXTDM5
entry per HDLC
entry per HDLC
entry per HDLC
Queue (global)
Queue (global)
Queue (global)
HDLC Address
HDLC Address
HDLC Address
global) SERVTIM0
global) SERVTIM0
global) SERVTIM0
EVENTQ0-7
EVENTQ0-7
EVENTQ0-7
Service Indicator
Service Indicator
Service Indicator
LUT (RTP) (1
LUT (RTP) (1
LUT (RTP) (1
Table (up to 16,
Table (up to 16,
Table (up to 16,
Structure (1 per
Structure (1 per
Structure (1 per
PCM channel)
PCM channel)
PCM channel)
Suppression
Suppression
Suppression
SILENCE0
SILENCE0
SILENCE0
TX Silence
TX Silence
TX Silence
TX RTP Connection
TX RTP Connection
TX RTP Connection
Structure (1 per
Structure (1 per
Structure (1 per
Structure (1 per
Structure (1 per
Structure (1 per
Connection)
Connection)
Connection)
Connection)
Connection)
Connection)
Connection
Connection
Connection
ASSEM 6-7
ASSEM 6-7
ASSEM 6-7
Assembly
Assembly
Assembly
ASSEM0-1
ASSEM0-1
ASSEM0-1
TX AAL2
TX AAL2
TX AAL2
Packet
Packet
Packet
Structure (1 per
Structure (1 per
Structure (1 per
TX RTP Header
TX RTP Header
TX RTP Header
Connection)
Connection)
Connection)
ASSEM2-5
ASSEM2-5
ASSEM2-5
(1 per SRC/DST
(1 per SRC/DST
IP Address pair)
IP Address pair)
Counter Source
Counter Source
Identification
Identification