ADC1175CIMTC National Semiconductor, ADC1175CIMTC Datasheet - Page 10

• Manufacturer Part Number: ADC1175CIMTC
• Description: 8-Bit/ 20MHz/ 60mW A/D Converter
• Manufacturer: National Semiconductor

www.national.com
Functional Description
The ADC1175 uses a new, unique architecture to achieve
7.2 effective bits at and maintains superior dynamic perfor-
mance up to
The analog signal at V
by V
Input voltages below V
sist of all zeroes. Input voltages above V
output word to consist of all ones. V
to the analog supply voltage, AV
0 to 4.0 Volts. V
positive than V
If V
are connected together, the nominal values of V
are 2.6V and 0.6V, respectively. If V
nected together and V
V
Data is acquired at the falling edge of the clock and the digi-
tal equivalent of the data is available at the digital outputs 2.5
clock cycles plus t
as the clock signal is present at pin 12. The Output Enable
pin OE, when low, enables the output pins. The digital out-
puts are in the high impedance state when the OE pin is
high.
Applications Information
1.0 The Analog Input
The analog input of the ADC1175 is a switch followed by an
integrator. The input capacitance changes with the clock
level, appearing as 4 pF when the clock is low, and 11 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than a fixed capacitance, choose an amplifier
that can drive this type of load. The CLC409, CLC440,
LM6152, LM6154, LM6181 and LM6182 have been found to
be excellent devices for driving the ADC1175. Do not drive
the input beyond the supply rails.
Figure 3 shows an example of an input circuit using the
LM6181. This circuit has both gain and offset adjustments. If
RT
RT
RT
is 2.3V.
and V
and V
RTS
1
RB
⁄
2
RB
the clock frequency.
are digitized to eight bits at up to 30 MSPS.
RT
are connected together and V
.
OD
should always be at least 1.0 Volt more
later. The ADC1175 will convert as long
RB
IN
RB
that is within the voltage range set
is grounded, the nominal value of
will cause the output word to con-
DD
, while V
RT
RT
has a range of 1.0 Volt
and V
RT
RB
will cause the
has a range of
RTS
RB
RT
and V
are con-
and V
RBS
RB
10
you desire to eliminate these adjustments, you should re-
duce the signal swing to avoid clipping at the ADC1175 out-
put that can result from normal tolerances of all system com-
ponents. With no adjustments, the nominal value for the
amplifier feedback resistor is 560
the inverting input should be changed to 1.5k and returned to
+5V rather than to the Offset Adjust potentiometer.
2.0 Reference Inputs
The reference inputs V
ence Bottom) are the top and bottom of the reference ladder.
Input signals between these two voltages will be digitized to
8 bits. External voltages applied to the reference input pins
should be within the range specified in the Operating Ratings
table (1.0V to AV
Any device used to drive the reference pins should be able to
source sufficient current into the V
current from the V
The reference ladder can be self-biased by connecting V
to V
tom reference voltages of approximately 2.6V and 0.6V, re-
spectively, with V
ure 3 . If V
analog ground, a top reference voltage of approximately
2.3V is generated. The top and bottom of the ladder should
be bypassed with 10µF tantalum capacitors located close to
the reference pins.
The reference self-bias circuit of Figure 3 is very simple and
performance is adequate for many applications. Superior
performance can generally be achieved by driving the refer-
ence pins with a low impedance source.
By forcing a little current into or out of the top and bottom of
the ladder, as shown in Figure 4 , the top and bottom refer-
ence voltages can be trimmed. The resistive divider at the
amplifier inputs can be replaced with potentiometers. The
LMC662 amplifier shown was chosen for its low offset volt-
age and low cost. Note that a negative power supply is
needed for these amplifiers as their outputs may be required
to go slightly negative to force the required reference
voltages.
RTS
and connecting V
RT
and V
DD
CC
RB
for V
RTS
= 5.0V. This connection is shown in Fig-
pin.
RT
are tied together, but V
RT
RB
(Reference Top) and V
and 0V to (AV
to V
RBS
RT
and the 5.1k resistor at
to provide top and bot-
pin and sink sufficient
DD
- 1.0V) for V
RB
RB
is tied to
(Refer-
RB
RT
).