PIC16CR58A Microchip Technology, PIC16CR58A Datasheet - Page 116

• Manufacturer Part Number: PIC16CR58A
• Description: ROM-Based 8-Bit CMOS Microcontroller Series
• Manufacturer: Microchip Technology

PIC16C6X
12.3
In Synchronous Master mode the data is transmitted in
a half-duplex manner i.e., transmission and reception
do not occur at the same time. When transmitting data
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RC6 and RC7 I/O pins to CK (clock) and
DT (data) lines respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTA<7>).
12.3.1
The USART transmitter block diagram is shown in
Figure 12-7. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR register is
loaded with new data from the TXREG register (if avail-
able). Once the TXREG register transfers the data to
the TSR register (occurs in one Tcycle), the TXREG
register is empty and interrupt flag bit TXIF (PIR1<4>)
is set. This interrupt can be enabled/disabled by set-
ting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF
will be set regardless of the status of enable bit TXIE
and cannot be cleared in software. It will clear only
when new data is loaded into the TXREG register.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. Status bit TRMT is a read
only bit which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll
this bit in order to determine if the TSR register is
empty. The TSR register is not mapped in data memory
so it is not available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started by
first loading the TXREG register and then setting
enable bit TXEN (Figure 12-13). This is advantageous
when slow baud rates are selected, since the BRG is
kept in reset when bits TXEN, CREN, and SREN are
clear. Setting enable bit TXEN will start the BRG, cre-
ating a shift clock immediately. Normally when trans-
mission is first started, the TSR register is empty, so a
transfer to the TXREG register will result in an immedi-
ate transfer to TSR resulting in an empty TXREG reg-
ister. Back-to-back transfers are possible.
DS30234D-page 116
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If, during a transmission, either bit CREN or bit
SREN is set the transmission is aborted and the DT pin
reverts to a hi-impedance state (for a reception). The
CK pin will remain an output if bit CSRC is set (internal
clock). The transmitter logic however, is not reset
although it is disconnected from the pins. In order to
reset the transmitter, the user has to clear enable bit
TXEN. If enable bit SREN is set (to interrupt an on
going transmission and receive a single word), then
after the single word is received, enable bit SREN will
be cleared, and the serial port will revert back to trans-
mitting since enable bit TXEN is still set. The DT line
will immediately switch from hi-impedance receive
mode to transmit and start driving. To avoid this, enable
bit TXEN should be cleared.
In order to select 9-bit transmission, bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to bit TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). If the TSR register
was empty and the TXREG register was written before
writing the “new” TX9D, the “present” value of bit TX9D
is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
1997 Microchip Technology Inc.