PIC16CR58A Microchip Technology, PIC16CR58A Datasheet - Page 96

• Manufacturer Part Number: PIC16CR58A
• Description: ROM-Based 8-Bit CMOS Microcontroller Series
• Manufacturer: Microchip Technology

PIC16C6X
11.4.2
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 11-15). The
more complex is the 10-bit address with a R/W bit
(Figure 11-16). For 10-bit address format, two bytes
must be transmitted with the first five bits specifying this
to be a 10-bit address.
FIGURE 11-15: 7-BIT ADDRESS FORMAT
FIGURE 11-16: I
11.4.3
All data must be transmitted per byte, with no limit to the
number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK) (Figure 11-17). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-14).
FIGURE 11-18: DATA TRANSFER WAIT STATE
DS30234D-page 96
S
R/W
ACK
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
ACK
S
R/W
- Start Condition
- Read/Write Pulse
- Acknowledge
SDA
SCL
ADDRESSING I
TRANSFER ACKNOWLEDGE
Start Condition
Acknowledge
Read/Write pulse
Condition
S
Start
S
MSb
2
C 10-BIT ADDRESS FORMAT
MSB
slave address
1
2
C DEVICES
Address
2
sent by slave
= 0 for write
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
acknowledgment
signal from receiver
LSb
R/W ACK
7
Sent by
Slave
R/W
8
ACK
9
byte complete
interrupt with receiver
Wait
State
FIGURE 11-17: SLAVE-RECEIVER
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move the
received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure 11-18. The slave will inherently stretch the clock,
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.
Transmitter
Output by
Output by
SCL from
Receiver
clock line held low while
interrupts are serviced
Master
1
Data
Data
Condition
Data
Start
2
S
ACKNOWLEDGE
3 8
acknowledgment
signal from receiver
1
1997 Microchip Technology Inc.
ACK
2
not acknowledge
9
acknowledge
Condition
Stop
8
Acknowledgment
Clock Pulse for
P
9