SM5902AF Nippon Precision Circuits Inc, SM5902AF Datasheet
SM5902AF
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SM5902AF Summary of contents
Page 1
... V wide operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination 4 bits) Approximately 3 longer (65 system clock pulses) continuous LOW-level reset - Digital audio interface (DIT) - 44-pin QFP package (0.8 mm pin pitch) SM5902AF NIPPON PRECISION CIRCUITS-1 ...
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... Package dimensions 44-pin QFP 1 44-pin QFP 2 0.80 Pinout (Top View) SM5902AF (Unit: mm) + 12.80 0.30 + 10.00 0.30 0.80 + 0.35 0.10 0.20 M 0.15 12.80 0.30 10.00 0.30 0.15 0.35 0.10 0.20 M VDD2 1 UC1 2 UC2 3 UC3 4 UC4 5 UC5 6 DIT 7 NTEST 8 CLK 9 VSS 10 YSRDATA 11 (1.40) + 0.60 0.20 (1.40) 0.60 0.20 NWE NCAS 28 A10/ NCAS2 27 YMCLK 26 YMDATA 25 YMLD 24 YDMUTE 23 NIPPON PRECISION CIRCUITS-2 ...
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... Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when in input mode) SM5902AF I/O Function - VDD supply pin Ip/O Microcontroller interface extension I/O 1 Ip/O Microcontroller interface extension I/O 2 Ip/O Microcontroller interface extension I/O 3 Ip/O Microcontroller interface extension I/O 4 Ip/O Microcontroller interface extension I Digital audio interface ...
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... Input current CLK (*3,4) Input leakage current (*2,3,4,5) (*2,5) (* CLK input frequency f DD1 DD2 SHPRF: Shock-proof, typical values are for DD1 DD2 SM5902AF (V = 0V, VDD1, VDD2 pin voltage = V SS Rating Unit - 0 125 ˚C 350 mW 255 ˚ ...
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... Pin function Pin name (*3) Pin function Pin name (*4) Pin function Pin name (*5) Pin function Pin name (*6) Pin function Pin name (*7) Pin function Pin name SM5902AF = ˚C) SS Symbol Condition I (*B)SHPRF ON DD (*B)Through mode H level V IH1 L level V IL1 V AC coupling ...
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... Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode operation. YSCK YSRDATA YLRCK SM5902AF = 4 ˚ - ˚C SS ...
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... Reset input (NRESET pin) Parameter First HIGH-level after supply voltage rising edge NRESET pulsewidth t Note. is the system clock (CLK) input (384fs) cycle time ns, (min) = 3.8 s when fs = 44.1 kHz CY NRST VDD NRESET SM5902AF Symbol Min MCWL MCWH ...
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... Input hold NWE pulsewidth NWE falling edge to NCAS falling edge Refresh cycle (fs = 44.1 kHz playback) Memory system ON Decode sequence operation (RDEN=H) t Note. is the system clock (CLK) input (384fs) cycle time. CY SM5902AF Symbol Condition Min load SCOW load SCOY load ...
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... (WRITE (READ) NWE (WRITE) t WCS The NWE terminal output is fixed HIGH during read timing. NCAS terminal output is fixed HIGH when selecting "DRAM2". NCAS2 terminal output is fixed HIGH when selecting "DRAM1". SM5902AF t RASL RCD CASL ...
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... DIT Interface (DIT pin) Parameter 0 data H level 0 data L level 1 data H level 1 data L level t Note. is the system clock (CLK) input (384fs) cycle time. CY DIT SM5902AF Symbol Condition load DI0H load DI0L load DI1H load DI1L when fs = 44.1 kHz. ...
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... YBLKCK Control YFCLK Input 1 YFLAG YMDATA YMCLK Micro- controller YMLD Interface ZSENSE DIT General UC1 to UC5 Port YDMUTE Control NRESET Input 2 NTEST SM5902AF Output Interface Attenuator Compression Through Mode Mode Decoder DRAM Interface NIPPON PRECISION CIRCUITS-11 Input Interface Input Buffer Encoder ...
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... Functional description SM5902AF has two modes of operation; shock- proof mode and through mode. Microcontroller interface Commands from the microcontroller are input using 3-wire serial interface inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). Write command format (Commands 80 to 86) ...
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... D5 D4 UC5WD D3 UC4WD D2 UC3WD D1 UC2WD D0 UC1WD SM5902AF Function Encode sequence start/stop Write address reset Decode sequence start/stop Read address reset MSDCN2=H, MSDCN1=H: 3-pair comparison start MSDCN2=H, MSDCN1=L: 2-pair comparison start MSDCN2=L, MSDCN1=H: Direct-connect start MSDCN2=L, MSDCN1=L: Connect operation stop Q data valid ...
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... D1 COMP5B D0 COMP4B When the number of compression bits is set incorrectly (2 or more bits are set all bits are set to 0), SM5902AF Function Attenuator enable Forced muting (changes instantaneously) Soft muting (changes smoothly when ON only) Includes noise shaper function when encoding Refer to " ...
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... When shockproof mode is ON, the Q data is specified according to the data output from the SM5902AF. SM5902AF Function Channel status and clock accuracy setting CP1= 0, CP2= 0 Level 2 (max ± 300 ppm) CP1= 0, CP2= 1 Level 3 (max ± CP1= 1, CP2= 0 Level 1 (max ± 50 ppm) ...
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... ENCOD Encode sequence operating state S4 DECOD Decode sequence operating state S3 QRDY Subcode Q data write-buffer write enable SM5902AF Function Input buffer memory overflow Function 90hex = 1001 0000 HIGH-level state Exceeded DRAM overflow Input buffer memory overflow Compare-connect sequence operating Encoding stopped Decoding stopped Refer to " ...
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... OR the output data from a pin configured as an output port using the 82H command.) Bit Name UC5RD S3 UC4RD S2 UC3RD S1 UC2RD S0 UC1RD SM5902AF Function 4M bits 2M bits 1M bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 4k bits 2k bits 1k bits 512 bits ...
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... Set Reset - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued SM5902AF - Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a disturbance has exceeded the RAM jitter margin. - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. ...
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... Meaning 91H Set bit 3 Reset SM5902AF - Indicates that the valid data residual has become 0 - When the VWA (final valid data's next address (address from which the next read would take place) - Whenever the above does not apply - Indicates a write to external DRAM overflow state - When the write address (WA) exceeds the read address (RA) ...
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... MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 0: Decode sequence stops 81H (Extension I/O port settings) 82H (Extension I/O port output data settings) SM5902AF -MSRACL When 1: Initializes the read address (RA) When 0: No operation - MSDCN2, MSDCN1 When 1 and 1: 3-pair compare-connect sequence ...
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... When 0 and 0: Sets FLAG6 on the falling edge of YFCLK when YFLAG=0 When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 SM5902AF - MUTE, SOFT, YDMUTE relationship When all mute inputs are 0, mute is released (noise shaper enable) When 1: Includes noise shaper function in com- pression-mode shockproof operation ...
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... DQ50 DQ51 0 DQ57 DQ58 DQ59 1 DQ65 DQ66 DQ67 then address 1001 is written again. Note that when shockproof mode is ON, the Q data is specified according to the data output from the SM5902AF. CRC S0 QD4 QD3 QD2 QD1 CTL3 ADR3 ADR2 ADR1 ADR0 DQ4 ...
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... Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. SM5902AF troller command 80H. This mode comprises the following 3 sequences. 3. The encoder, after the most suitable predicting filter type and quantization steps have been deter- mined, performs ADPCM encoding and then writes to external DRAM ...
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... YBLKCK Microcontroller data set Refer to Microcontroller interface VWA SM5902AF VWA 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV com- mand (80H). 3.When the WAQV command is received, the previ- ously latched WA is stored as the VWA. ...
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... When YFLAG=LOW 4 1 When YFLAG=HIGH SM5902AF encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depend- ing on the YFLGS flag and YFCKP flag (85H com- mand). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low ...
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... The SM5902AF supports three kinds of connect modes; 3-pair compare-connect, 2-pair compare- connect and direct connect. Note that the SM5902AF can also operate in 12-bit comparison connect mode using only the most sig- nificant 12 bits of data for connection operation. In 3-pair compare-connect mode, the final 6 valid ...
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... Data compression mode 4 bit 5 bit 6 bit Full bit SM5902AF - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued ...
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... When 85H generated WA CAS 3FE RA CAS 3FD Encode compression mode Decode compression mode (note) CAS-000 is connect data. SM5902AF The compression mode change is not performed immediately after input of the 85H command, but it is performed at the following timing. 001 002 3FF 3FE 3FF ...
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... But when the ATT flag is 0 (Datt = 256), there is no attenuation. set 1 Gain set 2 SM5902AF clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs (80 clock cycles). This jitter margin is the allowable difference between the system clock (CLK) divided by 384 (fs rate clock) and the YLRCK input clock ...
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... When the CMP12 flag is set to 1, the least signifi- cant 4 bits of the 16-bit comparison connection input data are discarded and comparison connec- tion is performed using the remaining 12 bits. SM5902AF Conversely, mute is released when the SOFT flag this case, the attenuation counter instanta- neously increases. The attenuation register takes on the value when the ATT flag was 1 ...
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... Preamble The SM5902AF starts with 0, so only the preamble patterns for leading symbol = 0 are used. Digital audio sample data and auxiliary audio The digital audio sample data is a 20-bit digitized audio signal. Auxiliary audio data, on the other hand, can be audio sample data of varying length. ...
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... Subframe parity The parity bit is used to indicate the detection of an odd number of bit errors set the number the digital audio interface 27-bit data is odd, SM5902AF ...
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... Timing charts Input timing (YSCK, YSRDATA, YLRCK) YSCK YSRDATA YLRCK Output timing (ZSCK, ZSRDATA, ZLRCK ZSCK ZSRDATA ZLRCK SM5902AF 1/(3fs ) 1/ NIPPON PRECISION CIRCUITS-33 ...
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... Write timing (with single DRAM) NRAS NCAS t RADS A0 to A10 (WRITE) NWE Write timing (with 2 DRAMs) NRAS NCAS1 (DRAM1 SELECT) NCAS2 (DRAM2 SELECT) t RADS (WRITE) NWE SM5902AF t RASL t t RDC CASL RADH CADS CADH t t CWDS CWDH t WEL t RASL ...
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... Read timing (with single DRAM) NRAS NCAS t RADS A0 to A10 (READ) NWE Read timing (with 2 DRAMs) NRAS NCAS1 (DRAM1 SELECT) NCAS2 (DRAM2 SELECT) t RADS (READ) NWE SM5902AF t RASL t t RCD CASL RADH CADS CADH t CRDS t OEL t RASL t t ...
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... When single DRAM is used, the DRAM OE pin should be tied LOW or controlled by the SM5902 NOE signal. note 2 When CXD 2517 (Sony) is used Set 85H of microcontroller command (option setting) as setting YFLAG take in; D5: YFLAGS= 1 D4: YFCKP= 0 SM5902AF SM5902 UC1 to UC5 DIT DRAM 1 NRAS ...
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... UC6 27 NOE / NCAS2 VDD pins The SM5902AF operates from supply volt- age, but a built-in level shifter is provided for use with external 5 V DRAM ICs. There are, therefore, 2 supply pins. VDD1 is the internal supply, and DIT pin The SM5902AF incorporates a digital audio inter- face output from pin DIT ...
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... Attenuation The SM5902AF supports attenuation level adjust- ments in steps 1/4 of the minimum level for smooth 16MDRAM The SM5902AF can use with up to 16MDRAM. (in case of SM5856A1F 2.) So you can get a long shock-proof time. SM5902AF mand, during normal operation. However, all other settings should remain unchanged while switching ...
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... SM5902AF NIPPON PRECISION CIRCUITS-39 ...
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... Customers shall not export, directly or indirect- ly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. SM5902AF reserves the right to make changes to the products described in this data sheet in order to NIPPON PRECISION CIRCUITS INC. ...