SM5902AF Nippon Precision Circuits Inc, SM5902AF Datasheet - Page 6

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SM5902AF

Manufacturer Part Number
SM5902AF
Description
compression and non compression type shock-proof memory controller
Manufacturer
Nippon Precision Circuits Inc
Datasheet

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Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input
AC characteristics
Standard voltage: V
Low-voltage: V
(*) Typical values are for fs = 44.1 kHz
System clock (CLK pin)
System clock input
Serial input (YSRDATA, YLRCK, YSCK pins)
Clock pulsewidth (HIGH level)
Clock pulsewidth (LOW level)
Last YSCK rising edge to YLRCK edge
YLRCK edge to first YSCK rising edge
data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode
operation.
YSCK pulsewidth (HIGH level)
YSCK pulsewidth (LOW level)
Clock pulse cycle
YLRCK pulse frequency
Parameter
YSRDATA setup time
YSRDATA hold time
YSCK pulse cycle
See note below.
DD1
Parameter
YSRDATA
YLRCK
= V
DD1
YSCK
CLK
DD2
= V
= 2.4 to 4.5 V, V
DD2
= 4.5 to 5.5 V, V
Symbol
t
t
CWH
t
CWL
CY
t
t
CWH
DS
Symbol
SS
t
t
BCWH
t
BCWL
t
t
t
t
BCY
DH
DS
BL
LB
= 0 V, Ta = -20 to 70 ˚C
t
SM5902AF
CY
SS
System clock
Condition
= 0 V, Ta = -40 to 85 ˚C
384fs
t
BCWH
t
Min
t
150
t
CWL
75
75
50
50
50
50
DH
fs
0
BL
t
BCY
Rating
Typ
t
BCWL
t
LB
NIPPON PRECISION CIRCUITS-6
Min
Max
26
26
56
3fs
fs
Rating
29.5
29.5
Typ
Unit
59
ns
ns
ns
ns
ns
ns
ns
0.5V
0.5V
0.5V
0.5V
DD
DD
DD
Memory system OFF
Memory system ON
DD
Max
125
125
250
(MSON=H)
(MSON=L)
Condition
Unit
ns
ns
ns

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