HCF40103BEY STMicroelectronics, HCF40103BEY Datasheet

HCF40103BEY

Manufacturer Part Number

HCF40103BEY

Description

IC DOWN COUNTER 8BIT BIN 16-DIP

Manufacturer

STMicroelectronics

Series

4000Br

Datasheet

1.HCF40103BEY.pdf (14 pages)

Specifications of HCF40103BEY

Logic Type

Binary Counter

Direction

Down

Number Of Elements

Number Of Bits Per Element

Reset

Asynchronous

Timing

Asynchronous/Synchronous

Count Rate

4.8MHz

Trigger Type

Positive Edge

Voltage - Supply

3 V ~ 20 V

Operating Temperature

-55°C ~ 125°C

Mounting Type

Through Hole

Package / Case

16-DIP (0.300", 7.62mm)

Counter Type

Binary

Counting Sequence

Down

Number Of Circuits

Logic Family

4010

Propagation Delay Time

600 ns, 260 ns, 190 ns

Supply Voltage (max)

20 V

Maximum Operating Temperature

+ 125 C

Minimum Operating Temperature

- 55 C

Function

8 Bit Binary Down Counter

Mounting Style

Through Hole

Operating Supply Voltage

3.3 V, 5 V, 9 V, 12 V, 15 V, 18 V

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

497-1341-5

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DESCRIPTION

HCF40103B is a monolithic integrated circuit

fabricated

technology available in DIP and SOP packages.

HCF40103B consists of an 8-stage synchronous

down counter with a single output that is active

when the internal count is zero. This device

contains a single 8-bit binary counter. It has

control inputs for enabling or disabling the clock,

for clearing the counter to its maximum count, and

for presetting the counter either synchronously or

asynchronously. All control inputs and the

CARRY-OUT/ZERO

active-low logics. In normal operation, the counter

is decremented by one count on each positive

transition of the CLOCK. Counting is inhibited

when the CARRY-IN/COUNTER ENABLE (CI/

PIN CONNECTION

September 2002

SYNCHRONOUS OR ASYNCHRONOUS

PRESET

MEDIUM -SPEED OPERATION :

CASCADABLE

QUIESCENT CURRENT SPECIF. UP TO 20V

5V, 10V AND 15V PARAMETRIC RATINGS

INPUT LEAKAGE CURRENT

100% TESTED FOR QUIESCENT CURRENT

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

= 100nA (MAX) AT V

=3.6MHz (Typ.) at V

Metal

DETECT

Oxide

= 18V T

= 10V

8-STAGE PRESETTABLE SYNCHRONOUS

Semiconductor

output

= 25°C

8 BIT BINARY DOWN COUNTERS

are

ORDER CODES

CE) input is high. The CARRY-OUT/ZERO

DETECT (CO/ZD) output goes low when the

count reaches zero if the CI/CE input is low, and

remains low for one full clock period. When the

SYNCHRONOUS PRESET ENABLE (SPE) input

is low, data at the JAM input is clocked into the

counter on the next positive clock transition

regardless of the state of the CI/CE input. When

the ASYNCHRONOUS PRESET ENABLE (APE)

input is low, data at the JAM inputs is

asynchronously forced into the counter regardless

of the state of the SPE, CI/CE, or CLOCK inputs.

JAM inputs J0-J7 represent a single 8 bit binary

word. When the CLEAR (CLR) input is low, the

counter is asynchronously cleared to its maximum

count (255

input. The precedent relationship between control

input is indicated in the truth table. If all control

PACKAGE

SOP

DIP

) regardless of the state of any other

DIP

HCF40103BEY

HCF40103BM1

TUBE

HCF40103B

HCF40103M013TR

SOP

T & R

1/14

Related parts for HCF40103BEY

HCF40103BEY Summary of contents

Page 1

... When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (255 input. The precedent relationship between control input is indicated in the truth table. If all control HCF40103B DIP SOP TUBE T & R HCF40103BEY HCF40103BM1 HCF40103M013TR ) regardless of the state of any other 10 1/14 ...

Page 2

HCF40103B inputs are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. IINPUT EQUIVALENT CIRCUIT FUNCTIONAL DIAGRAM TRUTH TABLES CONTROL INPUTS CLR APE SPE H ...

Page 3

LOGIC DIAGRAM LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7 HCF40103B 3/14 ...

Page 4

HCF40103B TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Input Current I P Power Dissipation per Package D Power Dissipation per Output Transistor T Operating Temperature op T Storage Temperature stg ...

Page 5

DC SPECIFICATIONS Symbol Parameter V (V) I Quiescent Current 0/5 L 0/10 0/15 0/20 V High Level Output 0/5 OH Voltage 0/10 0/15 V Low Level Output 5/0 OL Voltage 10/0 15/0 V High Level Input IH Voltage V Low ...

Page 6

HCF40103B DYNAMIC ELECTRICAL CHARACTERISTICS (T Symbol Parameter t t Propagation Delay Time PHL PLH Clock To Out t t Propagation Delay Time PHL PLH Carry In/counter Enable To Output t t Propagation Delay Time PHL PLH Asynchronous Preset Enable To ...

Page 7

TYPICAL APPLICATIONS DIVIDE BY "N" COUNTER MICROPROCESSOR INTERRUPT TIMER MICROPROCESSOR INTERRUPT TIMER SYNCHRONOUS CASCADING SYNCHRONOUS CASCADING * An Output spike (160ns 5V) occurs whenever two or DD more devices are cascaded in the parallel clocked mode because ...

Page 8

HCF40103B TEST CIRCUIT C = 50pF or equivalent (includes jig and probe capacitance 200K pulse generator (typically OUT WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/14 ...

Page 9

WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) HCF40103B 9/14 ...

Page 10

HCF40103B WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 10/14 ...

Page 11

WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) HCF40103B 11/14 ...

Page 12

HCF40103B DIM. MIN. a1 0. 12/14 Plastic DIP-16 (0.25) MECHANICAL DATA mm. TYP MAX. 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 inch MIN. TYP. ...

Page 13

SO-16 MECHANICAL DATA DIM. MIN 0 0. 9 3.8 G 4 mm. TYP MAX. MIN. 1.75 0.2 0.003 1.65 0.46 0.013 0.25 ...

Page 14

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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