IDT72V36110L10PF IDT, Integrated Device Technology Inc, IDT72V36110L10PF Datasheet - Page 34

• Manufacturer Part Number: IDT72V36110L10PF
• Description: IC FIFO SYNC 131KX36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36110L10PF

• Function: Synchronous
• Memory Size: 4.7M (131K x 36)
• Data Rate: 166MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 128Kx36
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36110L10PF; 800-1530

NOTE:
1. X = 15 for the IDT72V36100 and X = 16 for the IDT72V36110.
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW.
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Q
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
WCLK
WCLK
RCLK
0
D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
WEN
SEN
REN
- Q
PAE
PAF
1
LD
OR
, W
RT
HF
SI
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
BIT 0
t
t
t
ENS
LDS
DS
t
ENS
t
W
RTS
x+1
t
t
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
ENH
LDH
1
t
A
EMPTY OFFSET
t
t
ENH
HF
t
SKEW2
1
W1
TM
2
36-BIT FIFO
t
PAFS
2
t
A
BIT X
34
(1)
W
BIT 0
2
(4)
3
t
A
t
PAES
FULL OFFSET
W
3
(4)
t
4
A
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
W
OCTOBER 22, 2008
BIT X
t
ENH
t
t
4
LDH
DH
(4)
(1)
5
t
A
6117 drw20
6117 drw19
t
ENH
W
5