CY7C4211V-15AI Cypress Semiconductor Corp, CY7C4211V-15AI Datasheet

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... CY7C4201V/4211VCY7C4241V/4251VLow Voltage 256/512 x 9 Synchronous FIFOs Features ■ High-speed, low-power, first-in, first-out (FIFO) memories ❐ 256 x 9 (CY7C4201V) ❐ 512 x 9 (CY7C4211V) ■ High-speed 66-MHz operation (15-ns read/write cycle time) ■ Low power ( mA) CC ■ 3.3 V operation for low power consumption and easy integration into low-voltage systems ■ ...

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Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Pin Definitions .................................................................. 3 Functional Description ..................................................... 4 Architecture ...................................................................... 4 Resetting the FIFO ............................................................ 4 FIFO Operation ................................................................. 4 Programming .................................................................... 5 Programmable Flag (PAE, PAF) Operation ................ 6 Width ...

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Pin Configuration Selection Guide Description Maximum Frequency Maximum Access Time Minimum Cycle Time Minimum Data or Enable Set-up Minimum Data or Enable Hold Maximum Flag Delay Active Power Supply Current Commercial Pin Definitions Signal Name Description I/O D Data Inputs ...

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Pin Definitions (continued) Signal Name Description I/O PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value Almost Empty programmed into the FIFO. PAF Programmable O When PAF is LOW, the ...

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Programming When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C42X1V for writing or ...

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... PAF. LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4201V (256 – m) and CY7C4211V (512 – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...

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Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input control signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags ...

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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65 Ambient Temperature with Power Applied ........................................... –-55 Supply Voltage to Ground Potential..............–0 +5 Voltage Applied to ...

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Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Set-Up Time DS t Data ...

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Switching Waveforms t CLKH WCLK D – WEN1 WEN2 (if applicable) FF [11] t SKEW1 RCLK REN1,REN2 t CLKH RCLK t t ENS ENH REN1,REN2 EF Q – OLZ OE WCLK WEN1 WEN2 Notes 11. ...

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Switching Waveforms (continued) RS REN1, REN2 WEN1 [15] WEN2/LD EF,PAE FF,PAF − 8 Notes 13. The clocks (RCLK, WCLK) can be free-running during reset. 14. After reset, the outputs will be LOW and ...

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Switching Waveforms (continued) Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ENS WEN1 WEN2 (if applicable) t SKEW1 RCLK EF REN1, REN2 Q ...

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Switching Waveforms (continued) WCLK t DS DATAWRITE1 D – ENH WEN1 t ENS t t ENS ENH WEN2 (if applicable) [16] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q –Q ...

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Switching Waveforms (continued) NO WRITE WCLK [11] t SKEW1 D – WFF FF WEN1 WEN2 (if applicable) RCLK t ENH t ENS REN1, REN2 LOW DATA IN OUTPUT REGISTER Q – Figure ...

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... If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW. 22. PAF offset = m. 23. 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V 24 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...

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... WEN2/LD t ENS REN1, REN2 Q – Ordering Information Speed (ns) Ordering Code Package Name 256 x 9 Low Voltage Synchronous FIFO 15 CY7C4201V-15AXC 512 x 9 Low Voltage Synchronous FIFO 15 CY7C4211V-15AI CY7C4211V-15AXI Ordering Code Definitions Document #: 38-06010 Rev. *E Figure 14. Read Programmable Registers t CLKL t ENH t A UNKNOWN ...

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Package Diagrams Document #: 38-06010 Rev. *E Figure 15. 32-Pin TQFP (7X7X1.0 mm) CY7C4201V/4211V 51-85063 *C Page [+] Feedback ...

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... Added Pb-Free logo to top of front page, Inserted industrial temperature range into operating range, Added parts CY7C4251V-25AXC, CY7C4251V-15AXC, CY7C4241V-15AXC, CY7C4241V-15JXC, CY7C4241V-25XC, CY7C4231V-25AXC, CY7C4221V-15AI, CY7C4211V-15AXI, CY7C4201V-15AXC to ordering information. Added Contents, Updated package diagrams, Removed inactive parts from Ordering information table, Removed references to CY7C4421V and ...

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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...