CY7C4211V-15AI Cypress Semiconductor Corp, CY7C4211V-15AI Datasheet - Page 6

• Manufacturer Part Number: CY7C4211V-15AI
• Description: IC SYNC FIFO MEM 512X9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4211V-15AI

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in
Almost Empty Flag (PAE) and programmable Almost Full Flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
Table 1. Writing the Offset Registers
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred to
as n and determines the operation of PAE. PAE is synchronized
Table 2. Status Flags
Document #: 38-06010 Rev. *E
Notes
0
1 to n
(n+1) to 128
129 to (256−(m+1))
(256−m)
256
LD
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n=7 default value).
3. m = Full Offset (m=7 default value).
0
0
1
1
Table 1
[2]
WEN
0
1
0
1
[3]
CY7C4201V
or the default values are used, the programmable
to 255
WCLK
Number of Words in FIFO
[1]
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
0
1 to n
(n+1) to 256
257 to (512−(m+1))
(512−m)
512
[2]
Selection
[3]
CY7C4211V
to 511
to the LOW-to-HIGH transition of RCLK by one flip-flop and is
LOW when the FIFO contains n or fewer unread words. PAE is
set HIGH by the LOW-to-HIGH transition of RCLK when the
FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit register
and full offset most significant bit register is referred to as m and
determines the operation of PAF.
LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW
when the number of unread words in the FIFO is greater than or
equal to CY7C4201V (256 – m) and CY7C4211V (512 – m). PAF
is set HIGH by the LOW-to-HIGH transition of WCLK when the
number of available memory locations is greater than m.
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
CY7C4201V/4211V
PAF is synchronized to the
PAE
H
H
H
H
L
L
Page 6 of 19
EF
H
H
H
H
H
L
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