IDT72V271LA10PFG IDT, Integrated Device Technology Inc, IDT72V271LA10PFG Datasheet - Page 25

• Manufacturer Part Number: IDT72V271LA10PFG
• Description: IC FIFO SYNC 3.3V 10NS 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V271LA10PFG

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 32Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 72V271LA10PFG; 800-1523

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 16,384 and 32,768 for the IDT72V271LA with a 9-bit bus
width. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no
external logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with each single
FIFO. Figure 22 shows a depth expansion using two IDT72V261LA/
72V271LA devices.
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down")
until it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO's outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and TRCLK is the
RCLK period. Note that extra cycles should be added for the possibility
that the t
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
The IDT72V261LA can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all
For an empty expansion configuration, the amount of time it takes for OR
SKEW3
n
specification is not met between WCLK and transfer clock,
(N – 1)*(4*transfer clock) + 3*T
Dn
WEN
IR
WCLK
72V261LA
72V271LA
FWFT/SI
Figure 20. Block Diagram of 32,768 x 9 and 65,536 x 9 Depth Expansion
IDT
TRANSFER CLOCK
RCLK
RCLK
REN
OE
OR
Qn
GND
n
25
or RCLK and transfer clock, for the OR flag.
an empty depth expansion configuration. There will be no delay evi-
dent for subsequent words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one
until it finally moves into the first FIFO of the chain. Each time a free
location is created in one FIFO of the chain, that FIFO's IR line goes
LOW, enabling the preceding FIFO to write a word to fill it.
of the first FIFO in the chain to go LOW after a word has been read from
the last FIFO is the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
WCLK period. Note that extra cycles should be added for the possibility
that the t
clock, or WCLK and transfer clock, for the IR flag.
whichever is faster. Both these actions result in data moving, as quickly
as possible, to the end of the chain and free locations to the beginning
of the chain.
The "ripple down" delay is only noticeable for the first word written to
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR
The Transfer Clock line should be tied to either WCLK or RCLK,
SKEW1
WCLK
IR
WEN
Dn
specification is not met between RCLK and transfer
(N – 1)*(3*transfer clock) + 2 T
72V261LA
72V271LA
FWFT/SI
IDT
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
REN
OR
OE
Qn
JANUARY 30, 2009
WCLK
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
READ CLOCK
DATA OUT
WCLK
4673 drw 23
is the