IDT72V3670L10PF IDT, Integrated Device Technology Inc, IDT72V3670L10PF Datasheet - Page 13

• Manufacturer Part Number: IDT72V3670L10PF
• Description: IC FIFO SYNC II 36BIT 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3670L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 166MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 8Kx36
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3670L10PF; 800-1536

TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
4. As well as selecting parallel programming mode, one of the default values will
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
be loaded depending on the state of FSEL0 & FSEL1.
also be loaded depending on the state of FSEL0 & FSEL1.
LD
LD
LD
LD
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
IDT72V3660, 72V3670, 72V3680, 72V3690
IDT72V3640, 72V3650
FSEL1
FSEL1
FSEL1
FSEL1
H
H
H
H
H
H
H
H
L
L
L
L
X
X
L
L
L
L
X
X
FSEL0
FSEL0
FSEL0
FSEL0
H
H
H
H
H
H
H
H
L
L
L
L
X
X
L
L
L
L
X
X
Program Mode
Program Mode
Offsets n,m
Offsets n,m
Parallel
Parallel
Serial
Serial
1,023
255
127
255
127
511
511
63
31
15
63
31
15
7
3
7
(3)
(3)
(4)
(4)
TM
13
36-BIT FIFO
PROGRAMMING FLAG OFFSETS
72V3650/72V3660/72V3670/72V3680/72V3690 have internal registers for
these offsets. There are eight default offset values selectable during Master
Reset. These offset values are shown in Table 2. Offset values can also be
programmed into the FIFO in one of two ways; serial or parallel loading method.
The selection of the loading method is done using the LD (Load) pin. During
Master Reset, the state of the LD input determines whether serial or parallel flag
offset programming is enabled. A HIGH on LD during Master Reset selects serial
loading of offset values. A LOW on LD during Master Reset selects parallel
loading of offset values.
the current offset values. Offset values can be read via the parallel output port
Q
not possible to read the offset values in serial fashion.
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
be configured during the Master Reset cycle with either synchronous or
asynchronous timing for PAF and PAE flags by use of the PFM pin.
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous
PAF timing and Figure 18 for synchronous PAE timing.
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
19 for asynchronous PAF timing and Figure 20 for asynchronous PAE timing.
0
-Qn, regardless of the programming mode selected (serial or parallel). It is
Full and Empty Flag offset values are user programmable. The IDT72V3640/
In addition to loading offset values into the FIFO, it is also possible to read
Figure 3, Programmable Flag Offset Programming Sequence, summaries
The offset registers may be programmed (and reprogrammed) any time after
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 can
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008