HT45R36 Holtek Semiconductor, HT45R36 Datasheet - Page 19

• Manufacturer Part Number: HT45R36
• Description: C/R to F Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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Input/Output Ports
There are 25 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are
mapped to data memory addresses,12H, 14H, 16H and
18H, respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of the MOV A,[m] instruction. For
output operation, all the data is latched and remains un-
changed until the output latch is rewritten.
Each I/O line has its own control register, known as
PAC, PBC, PCC, PDC, to control the input/output con-
figuration. With this control register, the pin status as ei-
ther a CMOS output or Schmitt trigger input, but can be
reconfigured dynamically, i.e. on-the-fly, under software
control. To function as an input, the corresponding bit in
the control register must write 1 . The input source also
depends on the control register. If the control register bit
is 1 , the input will read the pad state. If the control reg-
ister bit is 0 , the contents of the latches will move to the
in t e r n a l b us . Th e la tter i s po s si bl e in the
When setup as output the output types are CMOS.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a device reset, the I/O ports will be initially all setup
as inputs, and will therefore be in a high state if the
Rev. 1.00
read-modify-write instruction.
Input/Output Ports
19
configuration options have selected pull-high resistors,
otherwise they will be in a floating condition. Each bit of
these input/output latches can be set or cleared by SET
[m].i and CLR [m].i (m=12H, 14H, 16H or 18H) in-
structions.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the de-
vice. The highest 7-bit of port D are not physically imple-
mented; on reading them a 0 is returned whereas writing
then results in a no-operation. See Application note.
There are 4 pull-high options available for PA, PB, PC
and PD individually. Once the pull-high option is se-
lected, I/O lines have pull-high resistors. Otherwise, the
pull-high resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PA0, PA1 and PA2 are pin-shared with INT0, INT1
and TMR pins, respectively.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
September 28, 2006
HT45R36