HT48R02M Holtek Semiconductor, HT48R02M Datasheet
HT48R02M
Related parts for HT48R02M
HT48R02M Summary of contents
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... Rev. 1.00 HT46R01M/HT46R02M HT48R01M/HT48R02M 1.5V Battery 8-Bit OTP MCU 6-level subroutine nesting Bit manipulation instruction Low voltage reset function 16-pin NSOP package ...
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... Note: The internal clock in the table is a fully integrated RC oscillator requiring no external components which can be used as the system clock. Block Diagram The following block diagram illustrates the main functional blocks. Pin Assignment www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Interrupt Data 8-bit Time I/O Memory Timer Base Ext ...
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... GND GND LX LX Note: I/T: Input type O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M OPT I/T O/T PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PAWK ADCR AN A/D channel 0 PAPU ST CMOS General purpose I/O ...
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... LX Note: I/T: Input type O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M OPT I/T O/T PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PAWK PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. ...
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... Low Voltage Reset 3 LVR I I/O Port Sink Current OL1 I I/O Port Source Current OH I PA7 Sink Current OL2 R Pull-high Resistance PH Note: The standby current (I Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M 0. +6.0V Storage Temperature ............................ 125 0. +0.3V Operating Temperature........................... Total............................................................ 100mA OH Test Conditions V ...
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... INT t Low Voltage Width to Reset LVR t Reset Delay Time RSTD Note =1/f SYS SYS 2. *For the resistor tolerance will influence the frequency a precision resistor is recommended. ERC www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Test Conditions Parameter V Conditions Ta= Ta= Ta=0~ Ta=0~ Ta=25 C, R=120k * ...
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... Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Test Circuit www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M OUT ...
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... VDD Start Voltage to Ensure V POR Power-on Reset VDD raising rate to Ensure RR VDD Power-on Reset Minimum Time for VDD Stays at t POR V to Ensure Power-on Reset POR www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Test Conditions Parameter V Conditions =0 =0 Test Conditions Parameter ...
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... RC oscillator is subdivided into four in- ternally generated non-overlapping clocks, T1~T4. The www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle ...
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... The acti- vated level is indexed by the Stack Pointer, SP, and is Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M neither readable nor writeable subroutine call or in- terrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a sub- ...
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... Timer/Event Counter inter- www.DataSheet4U.com rupt is enabled and the stack is not full. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M A/D interrupt vector This internal vector is used by the A/D converter. If A/D conversion complete , the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full ...
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... Program Memory ad- Instruction b10 TABRDC [m] PC10 TABRDL [m] 1 Note: HT46R01M/HT48R01M: PC9~PC8: Current program Counter bits HT46R02M/HT48R02M: PC10~PC8: Current program Counter bits @7~@0: Table Pointer TBLP bits Table Read Program Example - 1K ROM size tempreg1 db ? tempreg2 db ? www.DataSheet4U.com : : mov a,06h ...
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... The Data Memory can also be accessed through the memory pointer registers. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and ...
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... The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are pro- vided. These Memory Pointers are physically imple- mented in the Data Memory and can be manipulated in ...
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... C is also affected by a rotate through carry instruction. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag ...
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... PWM) TP Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M System Control Registers - CTRL0, CTRL1 These registers are used to provide control over various internal functions. Some of these include the PFD con- trol, PWM control, certain system clock options, the LXT ...
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... CTRL0 register - HT48R01M/HT48R02M Bit 7 Name R/W POR Bit 7 unimplemented, read as 0 Bit 6 PFDCS: PFD clock source 0: timer0 1: timer1 Bit 5~3 unimplemented, read as 0 Bit 2 PFDC: I/O or PFD 0: I/O 1: PFD Bit 1 LXTLP: LXT oscillator low power control function 0: LXT Oscillator quick start-up mode 1: LXT Oscillator Low Power Mode Bit 0 CLKMOD: system clock mode selection ...
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... Crystal/Resonator Oscillator - HXT Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer s specification. Crystal Oscillator C1 and C2 Values ...
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... C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or External LXT Oscillator Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M resonator manufacturer s specification. The external parallel feedback resistor, R vice the LXT oscillator must be used together with the HIRC oscillator. LXT Oscillator C1 and C2 Values ...
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... The ac- companying tables shows the relationship between the CLKMOD bit, the HALT instruction and the high/low fre- quency oscillators. The CLMOD bit can change normal or Slow Mode. www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M OSC1/OSC2 Configuration Operating Mode HXT Normal Run ...
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... TO and PDF flags. The PDF flag is cleared by a Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out ...
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... Watchdog Timer clock source, the SYS Watchdog Timer will cease to function. For systems that Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M operate in noisy environments, using the LIRC or the LXT as the clock source is therefore the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2 ...
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... LVR, where a full reset, similar to the RES reset is imple- mented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and ex- ternally: Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M WDTCK 9 ...
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... Note power-on delay, typical time=100ms RSTD Low Voltage Reset Timing Chart Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M will ignore the low supply voltage and will not perform a reset function. The actual V lected via configuration options. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal opera- tion is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1 ...
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... PAPU PB PBC PBPU CTRL0 CTRL1 PWM0 Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off The Timer Counter Prescaler will be cleared I/O ports will be setup as inputs Stack Pointer will point to the top of the stack ...
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... PAWK PAPU PB PBC PBPU CTRL0 CTRL1 Note: - not implemented u means unchanged x means unknown Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Power-on RES or LVR Reset Reset ...
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... PBPUn: Pull-high function enable 0: disable 1: enable Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M tors are implemented using weak PMOS transistors. Note that pin PA7 does not have a pull-high resistor se- lection. Port A Wake-up If the HALT instruction is executed, the device will enter the Sleep Mode, where the system clock will stop result- ing in power being conserved, a feature that is important for battery and other low-power applications ...
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... Note that even if the pin is setup as an external timer input the I/O function still remains. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M PFD Output The PFD function output is pin-shared with an I/O pin. The output function of this pin is chosen using the CTRL0 register. Note that the corresponding bit of the port control register, must setup the pin as an output to enable the PFD output ...
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... Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Generic Input/Output Ports PA7 NMOS Input/Output Port 29 December 18, 2009 ...
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... Reading from this register Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and deter- mines how the timer used ...
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... Note: If PWM0/PWM1 is enabled, then f Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Clock Structure for Timer/PWM/Time Base 8-bit Timer/Event Counter 0 Structure 8-bit Timer/Event Counter 1 Structure comes from (ignore T0S) SYS December 18, 2009 ...
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... Bit 2~0 T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection Timer internal clock= 000: f 001: f 010: f 011: f 100: f 101: f 110: f 111: f www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M T0M0 T0S T0ON R/W R/W R which is provided for Timer 0, the Time-Base and TP will be selected, overriding the T0S selection ...
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... Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 unimplemented, read as 0 www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M T1M0 T1S T1ON R/W R/W R/W ...
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... Control Register Operating Mode Select Bits for the Timer Mode Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M In this mode the internal clock is used as the timer clock. The timer input clock source is either f LXT oscillator. However, this timer clock source is fur- ...
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... At this point the enable bit will be automatically reset to zero and the Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will be- gin counting once a low to high transition has been re- ceived on the external timer pin and stop counting when the external timer pin returns to its original low level ...
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... Any pull-high resistor connected to this pin will remain valid even if the pin is used as a Timer/Event Counter input. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M PFD Function Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller ...
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... When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as the Time Base clock source is the same as the Timer/Event Counter clock source, care should be taken when programming. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M rupt request flag should first be set high before issuing the HALT instruction to enter the Sleep Mode. ...
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... PWM waveform, is di- vided into two groups. The first group which consists of Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table ...
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... Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M 6+2 PWM Mode PWM Register for 6+2 Mode 7+1 PWM Mode PWM Register for 7+1 Mode 39 December 18, 2009 ...
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... Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M the PWM data to appear on the pin. Writing a zero value will disable the PWM output function and force the out- put low. In this way, the Port data output registers can be used as an on/off control for the PWM function. Note ...
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... ADRH, utilises its full 8-bit contents. The low byte regis- ter utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M In the following table, D0~D11 is the A/D conversion data result bits. Bit Bit ...
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... Bit 5~3 PCR3, PCR2, PCR1, PCR0: A/D channel configuration 0: I/O 1: analog input n (n=0~3) If PCR0~PCR3 are all zero, the ADC circuit is power off to reduce power consumption Bit 2~0 ACS1 ~ ACS0: Select A/D channel 00: AN0 01: AN1 10: AN2 11: AN3 www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M ADRH ...
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... This A/D internal interrupt signal will direct the program flow to the associated A/D inter- nal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M ADONB R ...
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... Select which pins are to be used as A/D inputs and configure them as A/D input pins by correctly pro- gramming the PCR3~PCR0 bits in the ADCR register. Note that this step can be combined with Step 2 into a single ADCR register programming operation. Step 5 Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M A/D Clock Period (t ADCS2, ADCS2, ADCS2, ADCS1, ADCS1, ...
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... V /4096. The diagram show the ideal transfer function DD www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M between the analog input value and the digitised output value for the A/D converter. Note that to reduce the quantisation error, a 0.5 LSB off- set is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0 ...
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... STATUS,a mov a,acc_stack clr ADF reti Note: To power off ADC module necessary to set ADONB Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M ; disable ADC interrupt ; select A/D clock and ADONB=0 SYS ; setup ADCR register to configure Port as A/D inputs ; and select AN0 to be connected to the A/D converter ...
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... When this happens, the Program Counter, which stores the address of the next instruction to be exe- cuted, will be transferred onto the stack. The Program www.DataSheet4U.com Note: HT48R01M/HT48R02M haven t ADC interrupt Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. ...
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... Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Time Base Overflow Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M In cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences ...
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... TBF: Time Base event interrupt request flag 0: inactive 1: active Bit 4 ADF: A/D Conversion interrupt request flag 0: inactive 1: active Bit 3~2 unimplemented, read as 0 Bit 1 TBE: Time base event interrupt enable 0: disable 1: enable Bit 0 ADE: A/D Conversion interrupt enable 0: disable 1: enable Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M T1F T0F INTF T1E R/W R/W R/W R ...
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... It requires only three external compo- nents to provide a fixed output voltage of 3.0V for the ap- plication system. CMOS technology ensures ultra low supply current and makes it ideal for battery-operated applications powered from one or more cells. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M TBF R/W ...
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... CLRWDT instructions instructions 4 System oscillator configuration: HXT, HIRC, ERC, HIRC + LXT 5 LVR function: enable or disable 6 LVR voltage: 2.1V 7 RES or PA7 pin function 8 SST: 1024 or 2 clocks (determine t 9 Internal RC: 4MHz or 8MHz Application Circuits www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Options /4 SYS for HIRC/ERC) SST 51 December 18, 2009 ...
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... Typical Performance Characteristics HT7730 Output Voltage v.s Output Current HT7730 Efficiency v.s Output Current www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M HT7730 Start-Up& Hold-On Voltage HT7730 Load Transient Response (L=100mH, C OUT 52 =100mF, V =1.8V) IN December 18, 2009 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Description 55 Cycles Flag Affected ...
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... Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [ OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added ...
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... Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address ...
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... Operation Affected flag(s) HALT Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Complement Data Memory Each bit of the specified Data Memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1 s complement) ...
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... Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [ Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator. The contents of the Data Memory remain unchanged. ...
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... Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ACC Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper- ation ...
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... Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i ...
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... Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1 ...
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... Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched two cycle instruction. If the result is not 0 the program proceeds with the following instruction ...
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... Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator ...
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... Affected flag(s) XOR A,x Description Operation Affected flag(s) www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op- eration. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op- eration ...
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... Package Information 16-pin NSOP (150mil) Outline Dimensions MS-012 Symbol www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Dimensions in mil Min. Nom. 228 150 12 386 Max. 244 157 20 394 December 18, 2009 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 16N (150mil) Symbol A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness www.DataSheet4U.com Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Description 67 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 December 18, 2009 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length www.DataSheet4U.com B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M Description 68 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 December 18, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT46R01M/HT46R02M/HT48R01M/HT48R02M 69 December 18, 2009 ...