HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 10

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (bit 5 of the INTC0), caused by a Timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
The internal Timer/Event Counter 1 interrupt is initial-
ized by setting the Timer/Event Counter 1 interrupt re-
quest flag (bit 6 of the INTC0), caused by a Timer 1
overflow. When the interrupt is enabled, the stack is not
full and the T1F is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (T1F) will be
reset and the EMI bit cleared to disable further inter-
rupts.
USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC1) will be set.
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 10H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
Rev. 1.10
The access of the corresponding USB FIFO from PC
The USB suspend signal from the PC
The USB resume signal from the PC
USB Reset signal
Bit No.
Bit No.
3, 7
0
1
2
3
4
5
6
7
0
1
2
4
5
6
Label
Label
USBF
EADI
ET0I
ET1I
ADF
ESII
EMI
T0F
T1F
EEI
EIF
EUI
SIF
Controls the master (global) interrupt (1= enable; 0= disable)
Controls the external interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable)
External interrupt request flag (1= active; 0= inactive)
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
Unused bit, read as 0
Control the USB interrupt (1= enable; 0= disable)
Control the A/D converter interrupt (1= enable; 0=disable)
Control Serial interface interrupt (1= enable; 0= disable)
Unused bit, read as 0
USB interrupt request flag (1= active; 0= inactive)
A/D converter request flag (1= active; 0= inactive)
Serial interface interrupt request flag (1= active; 0= inactive)
INTC0 (0BH) Register
INTC1 (1EH) Register
10
When PC Host access the FIFO of the HT46RB50, the
corresponding request bit of USR is set, and a USB in-
terrupt is triggered. So user can easily determine which
FIFO is accessed. When the interrupt has been served,
the corresponding bit should be cleared by firmware.
When the HT46RB50 receives a USB Suspend signal
from the Host PC, the suspend line (bit0 of the USC) of
the HT46RB50 is set and a USB interrupt is also trig-
gered.
Also when the HT46RB50 receives a Resume signal
from the Host PC, the resume line (bit3 of the ) of the
HT46RB50 is set and a USB interrupt is triggered.
Whenever a USB reset signal is detected, a USB inter-
rupt is triggered.
The A/D converter interrupt is controlled by setting the
A/D interrupt control bit (EADI; bit 1 of the INTC1). When
the interrupt is enabled, the stack is not full and the A/D
conversion is finished, a subroutine call to location 14H
will occur. The related interrupt request flag ADF (bit5 of
the INTC1) will be reset and the EMI bit cleared to dis-
able further interrupts.
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 6 of the INTC1), that is caused by a recep-
tion or a complete transmission of an 8-bit data between
the HT46RB50 and an external device. The serial inter-
face interrupt is controlled by setting the Serial interface
interrupt control bit (ESII ; bit 2 of the INTC1). After the
Function
Function
September 7, 2006
HT46RB50