HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 9

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
Watchdog time-out flag (TO). It also records the status
information and controls the operation sequence. Ex-
cept for the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the HALT instruc-
tion.
The Z, OV, AC, and C flags reflect the status of the latest
operations. On entering the interrupt sequence or exe-
cuting a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status is important, and if the subroutine is likely to
corrupt the status register, the programmer should take
precautions and save it properly.
Rev. 1.10
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
Bit No.
6~7
0
1
2
3
4
5
Label
PDF
OV
AC
TO
C
Z
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by a system power-up or executing the CLR WDT instruction.
PDF is set by executing the HALT instruction.
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction.
TO is set by a WDT time-out.
Unused bit, read as 0
Status (0AH) Register
9
Interrupts
This device provides external interrupts (INT pin inter-
rupt, A/D Converter interrupt, Serial Interface interrupt)
and internal timer/event counter interrupts. The Interrupt
Control Register0 (INTC0;0BH) and interrupt control
register1 (INTC1:1EH) both contain the interrupt control
bits that are used to set the enable/disable status and in-
terrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 or INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts can are triggered by a falling edge
transition of INT), and the related interrupt request flag
(EIF; bit4 of the INTC0) is set as well. After the interrupt
is enabled, the stack is not full, and the external interrupt
is active (INT pin), a subroutine call at location 04H oc-
curs. The interrupt flag (EIF) and EMI bits are all cleared
to disable other maskable interrupts.
Function
September 7, 2006
HT46RB50