CY2412 Cypress Semiconductor, CY2412 Datasheet
CY2412
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CY2412 Summary of contents
Page 1
... MHz, 13.5 MHz, 54 MHz (3.3V) Cypress specification Φ OUTPUT DIVIDERS VCO P PLL VDD VSS • 3901 North First Street CY2412 Output Frequencies VCXO Profile Linear Pin Configuration CY2412-1,-3 8-pin SOIC CLKC CLKB 1 8 XIN 7 2 VDD CLKA 6 VCXO 3 5 VSS 4 , • ...
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... Parallel resonance, funda- mental mode, AT cut Fundamental mode Ratio used because typical R values are much less than the maximum spec. No external series resistor as- sumed High side NOM Low side NOM CY2412 Pin Description Condition Min. Typ. Max. Unit – 13.5 – – 14 – ...
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... Duty Cycle is defined in Figure 1, 50 Clock Edge Rate, Measured from 20 pF. See Figure 2. DD, LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD, LOAD Peak to Peak period jitter CY2412 Max. Unit 7.0 V 125 °C 125 ° 0 ...
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... SOIC–Tape and Reel CY2412SC-3 8-pin SOIC CY2412SC-3T 8-pin SOIC–Tape and Reel Lead-free CY2412SXC-1 8-pin SOIC CY2412SXC-1T 8-pin SOIC–Tape and Reel CY2412SXC-3 8-pin SOIC CY2412SXC-3T 8-pin SOIC–Tape and Reel Document #: 38-07227 Rev DataSheet U .com t1 t2 CLK ...
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... SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] CY2412 MAX. ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] ...
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... Description of Change 10/28/01 SZV Change from Spec number: 38-00898 to 38-07227 03/14/02 CKN Added CY2412-2 to data sheet 08/06/02 CKN Removed CY2412-2 from the datasheet. Added CY2412-3 to data sheet 12/14/02 RBI Power-up requirements added to Operating Conditions Information RGL Added lead-free for CY2412-1 and CY2412-3 devices CY2412 Page ...