IDT72205LB15JI IDT, Integrated Device Technology Inc, IDT72205LB15JI Datasheet - Page 9

IC FIFO 256X18 SYNC 15NS 68-PLCC

IDT72205LB15JI

Manufacturer Part Number
IDT72205LB15JI
Description
IC FIFO 256X18 SYNC 15NS 68-PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT72205LB15JI

Function
Synchronous
Memory Size
4.6K (256 x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Configuration
Dual
Density
4.5Kb
Access Time (max)
10ns
Word Size
18b
Organization
256x18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
60mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
68
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72205LB15JI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72205LB15JI
Manufacturer:
IDT
Quantity:
253
Part Number:
IDT72205LB15JI8
Manufacturer:
IDT
Quantity:
253
NOTE:
1. t
NOTE:
1. t
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
D
edge of RCLK and the rising edge of WCLK is less than t
0
WCLK
edge of WCLK and the rising edge of RCLK is less than t
SKEW1
RCLK
WCLK
0
SKEW2
RCLK
- Q
- D
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
17
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
t
ENS
t
OLZ
t
SKEW1
t
t
ENH
t
CLKH
CLKH
(1)
t
WFF
t
t
A
REF
t
SKEW1
OE
SKEW2
t
CLK
, then FF may not change state until the next WCLK edge.
, then EF may not change state until the next RCLK edge.
t
DATA IN VALID
CLK
Figure 5. Write Cycle Timing
Figure 6. Read Cycle Timing
NO OPERATION
t
SKEW2
t
t
CLKL
t
CLKL
DS
(1)
t
ENS
9
TM
VALID DATA
t
t
ENH
DH
t
t
REF
WFF
t
OHZ
COMMERCIAL AND INDUSTRIAL
NO OPERATION
TEMPERATURE RANGES
OCTOBER 22, 2008
2766 drw 07
2766 drw 08

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