ADP1876ACPZ-R7 Analog Devices, Inc., ADP1876ACPZ-R7 Datasheet - Page 19

• Manufacturer Part Number: ADP1876ACPZ-R7
• Description: 600 Khz Dual Output Synchronous Buck Pwm Controller With Linear Regulator
• Manufacturer: Analog Devices, Inc.

Data Sheet
Select an input bulk capacitor based on its ripple current rating.
First, determine the duty cycle of the output.
The input capacitor rms ripple current is given by
where:
I
D is the duty cycle.
The minimum input capacitance required for a particular load is
where:
V
R
If an MLCC capacitor is used, the ESR is near 0, then the
equation is simplified to
The capacitance of MLCC is voltage dependent. The actual
capacitance of the selected capacitor must be derated according to
the manufacturer’s specification. In addition, add more bulk
capacitance, such as by using electrolytic or polymer capacitors,
as necessary for large step load transients. Make sure the
current ripple rating of the bulk capacitor exceeds the
maximum input current ripple of a particular design.
INPUT FILTER
Normally a 0.1 µF (or greater value) bypass capacitor from the
input pin (VIN) to AGND is sufficient for filtering any unwanted
switching noise. However, depending on the printed circuit
board (PCB) layout, some switching noise can enter the
internal circuitry; therefore, it is recommended to have a low-
pass filter at the VIN pin. Connecting a resistor, between 2 Ω
and 5 Ω, in series with VIN and a 1 µF ceramic capacitor
between VIN and AGND creates a low-pass filter that effectively
filters out any unwanted glitches caused by the switching regulator.
Note that the input current can be larger than 100 mA when
driving large MOSFETs. A 100 mA current across a 5 Ω resistor
creates a 0.5 V drop, which is the same voltage drop in VCCO.
In this case, a lower resistor value is desirable.
O
ESR
PP
is the output current.
is the desired input ripple voltage.
is the equivalent series resistance of the capacitor.
C
C
D =
I
RMS
IN
IN
,
,
MIN
MIN
V
=
V
OUT
IN
I
=
O
=
(
V
I
D
O
PP
V
Figure 30. Input Filter Configuration
1 ( D
IN
×
−
−
V
I
2Ω TO 5Ω
D
O
I
PP
O
1 (
×
)
1µF
×
×
−
D
D
f
D
1 (
SW
×
)
−
R
D
ESR
VIN
AGND
ADP1876
)
)
f
SW
ADP1876
Rev. A | Page 19 of 24
BOOST CAPACITOR SELECTION
To lower system component count and cost, the
an integrated rectifier (equivalent to the boost diode) between
VCCO and BSTx. Choose a boost ceramic capacitor with a
value between 0.1 µF and 0.22 µF; this capacitor provides the
current for the high-side driver during switching.
INDUCTOR SELECTION
The output LC filter smoothes the switched voltage at SWx.
For most applications, choose an inductor value such that
the inductor ripple current is between 20% and 40% of the
maximum dc output load current. Generally, a larger inductor
current ripple generates more power loss in the inductor and
larger voltage ripples at the output. Check the inductor data
sheet to make sure that the saturation current of the inductor
is well above the peak inductor current of a particular design.
Choose the inductor value by using the following equation:
where:
L is the inductor value.
f
V
V
∆I
OUTPUT CAPACITOR SELECTION
Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output voltage
ripple. The impedance comprises the capacitive impedance plus
the nonideal parasitic characteristics, the equivalent series resis-
tance (ESR), and the equivalent series inductance (ESL). The
output voltage ripple can be approximated by
where:
∆V
∆I
R
the parallel combination of ESR of all output capacitors).
L
(or the parallel combination of ESL of all capacitors).
Solving C
SW
ESL
ESR
OUT
IN
L
L
OUT
is the switching frequency.
is the input voltage.
is the inductor ripple current.
is the inductor ripple current.
is the equivalent series inductance of the output capacitor
is the equivalent series resistance of the output capacitor (or
C
L
is the output voltage.
∆
is the output ripple voltage.
OUT
V
=
OUT
V
OUT
f
≅
IN
SW
≅
8
in the previous equation yields
−
∆
×
f
∆
V
I
SW
∆
L
I
OUT
L
I
×
L




R
∆
×
ESR
V
V
V
OUT
OUT
IN
+
−
8
f
∆
SW
I
L
R
×
1
ESR
C
1
OUT
−
4
∆
+
I
L
4
f
f
SW
SW
ADP1876
×
ADP1876
×
L
L
ESL
ESL




has