ADP1876ACPZ-R7 Analog Devices, Inc., ADP1876ACPZ-R7 Datasheet - Page 8

• Manufacturer Part Number: ADP1876ACPZ-R7
• Description: 600 Khz Dual Output Synchronous Buck Pwm Controller With Linear Regulator
• Manufacturer: Analog Devices, Inc.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADP1876
Mnemonic
EN1
VIN
VINLDO
VOUTLDO
VCCO
VDL
AGND
NC
EN2
FB2
COMP2
RAMP2
SS2
PGOOD2
ILIM2
BST2
Description
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn it off. Tie EN1
to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and
tie the midpoint to this pin.
Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as
possible and PGNDx.
Input for Independent Linear Dropout (LDO) Regulator.
Output for Independent LDO Regulator.
Output of the Internal LDO. The internal circuitry and gate drivers are powered from VCCO. Bypass VCCO to AGND
with a 1 μF or larger ceramic capacitor. The VCCO output is always active, even during fault conditions, and it
cannot be turned off even when EN1 or EN2 is low. For operation at VIN below 5 V, VIN can be jumped to VCCO. Do
not use the VCCO to power any other auxiliary system load.
Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 μF ceramic capacitor. Connect VCCO to VDL.
Analog Ground.
No connect. Do not connect to this pin.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie EN2
to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and
tie the midpoint to this pin.
Output Voltage Feedback for Channel 2.
Compensation Node for Channel 2. Output of the Channel 2 error amplifier. Connect a series resistor/capacitor
network from COMP2 to AGND to compensate the regulation control loop.
Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The
voltage at RAMP2 is 0.2 V during operation. This pin is high impedance when the channel is disabled.
Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is
internally pulled up to 3.2 V through a 6.5 µA current source.
Open-Drain Power-Good Indicator Logic Output at PGOOD2. An internal 12 kΩ resistor is connected between
PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An
external pull-up resistor is not required.
Current-Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set
the current-limit offset. For accurate current-limit sensing, connect ILIM2 to a current sense resistor at the source of
the low-side MOSFET.
Boot Strapped Upper Rail of High-Side Internal Driver for Channel 2. Connect a 0.1 µF to 0.22 µF multilayer ceramic
capacitor (MLCC) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. CONNECT THE BOTTOM EXPOSED PAD OF THE
VOUTLDO
LFCSP PACKAGE TO SYSTEM AGND PLANE.
VINLDO
VCCO
AGND
VDL
EN1
VIN
NC
1
2
3
4
5
6
7
8
Figure 3. Pin Configuration
Rev. A | Page 8 of 24
(Not to Scale)
ADP1876
TOP VIEW
24 SW1
23 DH1
22 PGND1
21 DL1
20 DL2
19 PGND2
18 DH2
17 SW2
Data Sheet