IDT72V265LA10PF IDT, Integrated Device Technology Inc, IDT72V265LA10PF Datasheet - Page 24

• Manufacturer Part Number: IDT72V265LA10PF
• Description: IC FIFO SS 16384X18 10NS 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA10PF

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 6.5ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA10PF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
control signals of multiple devices. Status flags can be detected from
any one device. The exceptions are the EF and FF functions in IDT
Standard mode and the IR and OR functions in FWFT mode. Because
of variations in skew between RCLK and WCLK, it is possible for EF/FF
deassertion and IR/OR assertion to vary by one cycle between FIFOs. In
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
Word width may be increased simply by connecting together the
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
72V255LA
72V265LA
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
24
0
n
- Qm
IDT Standard mode, such problems can be avoided by creating composite
flags, that is, ANDing EF of every FIFO, and separately ANDing FF of
every FIFO. In FWFT mode, composite flags can be created by ORing
OR of every FIFO, and separately ORing IR of every FIFO.
72V265LA devices. D0 - D17 from each device form a 36-bit wide input
bus and Q0-Q17 from each device form a 36-bit wide output bus. Any
word width can be attained by adding additional IDT72V255LA/72V265LA
devices.
Figure 23 demonstrates a width expansion using two IDT72V255LA/
72V255LA
72V265LA
FIFO
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Qm
+1
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
OCTOBER 22, 2008
4672 drw 22
GATE
(1)