IDT72V265LA10PF IDT, Integrated Device Technology Inc, IDT72V265LA10PF Datasheet - Page 8

• Manufacturer Part Number: IDT72V265LA10PF
• Description: IC FIFO SS 16384X18 10NS 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA10PF

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 6.5ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA10PF

TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
PROGRAMMING FLAG OFFSETS
IDT72V255LA/72V265LA has internal registers for these offsets. Default
settings are stated in the footnotes of Table 1 and Table 2. Offset values can
be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines whether
serial or parallel flag offset programming is enabled. A HIGH on LD during
Master Reset selects serial loading of offset values and in addition, sets a
default PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary), and a default PAF offset value of 3FFH (a threshold 1,023
words from the full boundary). A LOW on LD during Master Reset selects
parallel loading of offset values, and in addition, sets a default PAE offset
TABLE 2 — STATUS FLAGS FOR FWFT MODE
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
Full and Empty Flag offset values are user programmable. The
Words in
FIFO
Number of
Words in
FIFO
Number of
(1)
4,098 to (8,193–(m+1))
(8,192–m)
4,097 to (8,192–(m+1))
(8,193–m) to 8,192
(n + 1) to 4,096
(n + 2) to 4,097
72V255LA
72V255LA
1 to n+1
1 to n
8,192
8,193
0
(2)
0
to 8,191
(1)
(1)
(2)
8
value of 07FH (a threshold 127 words from the empty boundary), and a
default PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
the current offset values. It is only possible to read offset values via parallel
read.
rizes the control pins and sequence for both serial and parallel program-
ming modes. For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming
has been selected.
In addition to loading offset values into the FIFO, it also possible to read
Figure 4, Programmable Flag Offset Programming Sequence, summa-
The offset registers may be programmed (and reprogrammed) any time
8,194 to (16,385–(m+1))
(16,384–m)
(16,385–m)
8,193 to (16,384–(m+1))
(n + 1) to 8,192
(n + 2) to 8,193
72V265LA
72V265LA
1 to n+1
1 to n
16,384
16,385
0
0
(2)
(2)
(1)
to 16,383
to 16,384
(1)
(2)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FF PAF
FF PAF
H
H
H
H
H
H
L
L
L
L
L
L
OCTOBER 22, 2008
H
H
H
H
L
L
H
H
H
H
L
L
HF
HF
H
H
H
L
L
L
H
H
H
L
L
L
PAE EF
PAE EF
H
H
H
H
H
H
H
H
L
L
L
L
4672 drw 05
H
H
H
H
H
H
L
L
L
L
L
L