ST62T45B STMicroelectronics, ST62T45B Datasheet
ST62T45B
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ST62T45B Summary of contents
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... System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY OTP DEVICE (Bytes) ST62T45B 3884 ST62E45B March 1998 8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER with 7-bit (See end of Datasheet for Ordering Information) EPROM I/O Pins (Bytes 3884 ST62T45B/E45B PQFP52 CQFP52W Rev. 2.3 1/72 1 ...
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... ST62T45B/E45B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 www.DataSheet4U.com 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2 ...
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ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST62P45B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... EPROM/OTP versions only) common core is surrounded by a number of on- chip peripherals. The ST62E45B is the erasable EPROM version of the ST62T45B device, which may be used to em- ulate the ST62T45B device, as well as the respec- tive ST6245B ROM devices. 8-BIT A/D CONVERTER DATA ROM USER ...
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... ST62T45B/E45B INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions.OTP devices offer all the advantages of user programmability at low cost, ...
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... In output mode, the TIMER pin outputs the data bit when a time-out occurs.The user can select as option the availability of an on- chip pull-up at this pin. ST62T45B/E45B 7/72 6 ...
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... ST62T45B/E45B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram PROGRAM SPACE www.DataSheet4U.com 0000h PROGRAM MEMORY 0FF0h INTERRUPT & RESET VECTORS ...
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... EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for SGS-THOMSON, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted. ST62T45B/E45B Figure 4. ST62E45B/T45B Program Memory Map 0000h * RESERVED 007Fh ...
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... Program memory. 1.3.3.2 Data RAM/EEPROM In ST62T45B and ST62E45B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the pe- ...
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... ST62T45B/E45B Write Only - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0 PROGRAM SPACE ADDRESS READ DATA SPACE ADDRESS : 40h-7Fh IN INSTRUCTION DATA SPACE ADDRESS : 59h 1 ...
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... DRBR is not affected. In DRBR Register, only 1 bit must be set. Other- wise two or more pages are enabled in parallel, producing errors. Table 4. Data RAM Bank Register Set-up DRBR 00h 01h 02h 08h 10h other ST62T45B/E45B None EEPROM Page 0 EEPROM Page 1 Not available RAM Page 2 Reserved ...
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... The image regis- ter must be written to first so that interrupt oc- curs between the two instructions, the EECTL will not be affected The number of available 64-byte banks ( device dependent. ST62T45B/E45B Dataspace addresses. Banks 0 and 38h-3Fh 30h-37h ...
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... ST62T45B/E45B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle resetting E2PAR2 without programming the EEPROM ...
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... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V programming flow of the ST62T45B/E45B is de- scribed in the User Manual of the EPROM Pro- gramming Board. The MCUs can be programmed ST62E4xB EPROM programming tools available from SGS-THOMSON ...
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... ST62T45B/E45B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally www ...
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... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T45B/E45B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...
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... ST62T45B/E45B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 Main Oscillator The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator. Figure 8 illustrates various possible oscillator con- www ...
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... Start/Stop bit in the oscillator status/control register. OSC32KHz OSC32KHz f /13 INT START EOSCI OSCEOC X STOP INT ST62T45B/E45B 7 S 500ms elapsed time (providing /13 MUX DIV 2 ...
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... ST62T45B/E45B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...
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... Figure 12. Reset and Interrupt Processing and DD rises OSC 300k RESET 2.8k POWER ON RESET WATC HDOG RESET ST62T45B/E45B RESET JP JP:2 BYTES/4 CYCLES RESET VECTOR INITIALIZAT ION ROUTINE RETI: 1 BYTE/2 CYCLES RETI ST6 CK INTERNAL RESET COUNTE R RESET VA0200B VA00181 ...
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... ST62T45B/E45B RESETS (Cont’d) Table 6. Register Reset Status Register EEPROM Control Register Port Data Registers Port A,B Direction Register Port A,B Option Register Interrupt Option Register www.DataSheet4U.com SPI Registers LCD Mode Control Register 32kHz Oscillator Register Port C Direction Register Port C Option Register Register ...
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... The STOP instruction is interpreted as a WAIT in- struction, and the Watchdog continues to count- down. When the MCU exits STOP mode (i.e. when an in- terrupt is generated), the Watchdog resumes its activity. Stop Mode Watchdog ST62T45B/E45B Recommended Optio ns “SOFTWARE WATCHDOG” “HARDWARE WATCHDOG” 23/72 22 ...
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... ST62T45B/E45B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR) . This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits T5, and the SR bit are all set to “ ...
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... The software activation option should be chosen only when the Watchdog counter used as a timer. To ensure the Watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH ST62T45B/E45B 25/72 24 ...
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... ST62T45B/E45B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are ex- ecuted after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first Figure 15 ...
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... Table 9. Interrupt Option Register Description 3 (FF4h-FF5h) 4 (FF2h-FF3h) GEN 5 (FF0h-FF1h) ESB LES OTHERS ST62T45B/E45B SET Enable all interrupts CLEARED Disable all interrupts Rising edge mode on inter- SET rupt source #2 Falling edge mode on inter- CLEARED rupt source #2 Level-sensitive mode on in- SET terrupt source #1 ...
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... ST62T45B/E45B IINTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call procedure, indeed the user can consider the inter- rupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...
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... GEN D4h ETI D7h D1h EAI C2h ALL C0h-C4h ORPAn-DRPAn C1h-C5h ORPBn-DRPBn C6h-CFh ORPCn-DRPCn DBh EOSCI ST62T45B/E45B sources available on Interrupt Masked Interrupt Source source All Interrupts, excluding NM I All TMZ: TIMER Overflow source 3 EOC: End of Conversion source 4 End of Transmission source 1 PAn pin ...
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... ST62T45B/E45B INTERRUPTS (Cont’d) Figure 17. Interrupt Block Diagram www.DataSheet4U.com NMI FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B PORT C PBE Bits 30/72 29 CLK FF SPI CLK Q CLR I 1 CLK IOR bit 5 (ESB) TMZ TIMER1 ETI TMZ TIMER2 ETI OSCEOC OSC32kHz ...
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... Watchdog), the MCU enters a normal reset proce- dure interrupt is generated during WAIT mode, the MCU’s behaviour depends on the state ST62T45B/E45B of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following para- graphs ...
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... ST62T45B/E45B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state ...
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... RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pull- ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. RESET DATA DIRECTION REGISTER DATA REGISTER OPTION REGISTER ST62T45B/E45B INPUT/OUTPUT VA00413 33/72 32 ...
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... ST62T45B/E45B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table 11 illustrates the various port configurations which can be selected by user soft- ware ...
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... Interrupt 010* pull-up Input pull-up (Reset 000 state) Output 100 Open Drain Output 110 Push-pull ST62T45B/E45B Input 011 Analog Input 001 Output 101 Open Drain Output 111 Push-pull 35/72 34 ...
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... ST62T45B/E45B I/O PORTS (Cont’d) Table 12. I/O Port configuration for the ST62T45B/E45B MODE Input www.DataSheet4U.com Input with pull up (Reset state except for PC0-PC7) Input with pull up with interrupt Analog Input Open drain output 5mA Open drain output 20mA Push-pull output 5mA Push-pull output 20mA Note 1 ...
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... DR Mode 0 Input With pull-up, no interrupt 1 Input No pull-up, no interrupt 0 Input With pull-up and with interrupt 1 Input LCD segment (Reset state) X Output Open-drain output X Output Push-pull output PID PP/OD OPR 1 DR MUX 0 PID DR PID DR ST62T45B/E45B Option OUT IN SYNCHRONOUS SERIAL I/O CLOCK VR01661F 37/72 36 ...
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... ST62T45B/E45B I/O PORTS (Cont’d) 4.1.5 I/O Port Option Registers ORA/B/C (CCh PA, CDh PB, CFh PC) Read/Write 7 Px7 Px6 Px5 Px4 Bit 7-0 = Px7 - Px0 : Port Option Register bits. www.DataSheet4U.com 4.1.6 I/O Port Data Direction Registers DDRA/B/C (C4h PA, C5h PB, C6h PC) Read/Write 7 Px7 Px6 Px5 Px4 Bit 7-0 = Px7 - Px0: Port Data Direction Registers bits ...
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... PS2/PS1/PS0 bits in the control register. Figure 21 illustrates the Timer’s working principle. 7-BIT PRESCALER BIT1 BIT2 BIT3 8-1 MULTIPLEXER BIT2 BIT1 BIT3 BIT4 8-BIT COUNTER ST62T45B/E45B divided by 12 (TIMER 1 & ex- INT BIT4 BIT5 BIT6 PS0 PS1 PS2 BIT7 BIT5 BIT6 VA00186 ...
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... ST62T45B/E45B Figure 22. TIMER 1 Block Diagram PSC www.DataSheet4U.com TIMER Figure 23. TIMER 2 Block Diagram . f 12 INT 40/72 39 DATABUS COUNTER 4 SELECT SYNCHRONIZATION LOGIC DATA BUS 8-BIT 5 4 SELECT 3 PSC 8-BIT STATUS/CONTROL ...
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... TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time. Timer Function Event Counter Gated Input Output “0” Output “1” ST62T45B/E45B 12). INT 41/72 40 ...
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... ST62T45B/E45B TIMER 1& 2 (Cont’d) 4.2.5 TIMER 1 Registers Timer Status Control Register (TSCR) Address: 0D4h — Read/Write 7 TMZ ETI TOUT DOUT Bit 7 = TMZ: Timer Zero bit www.DataSheet4U.com A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count ...
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... Table 16. Prescaler Division Factors 0 D4 PSI PS2 PS1 PS0 Timer Counter Register (TCR) Address: 0D6h — Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D5h — Bit 7 = D7: Always read as ”0”. Bit 6-0 = D6-D0 : Prescaler Bits. ST62T45B/E45B PS2 PS1 PS0 ...
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... ST62T45B/E45B 4.3 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device de- pendent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock fre- quency of 8MHz). The ADC converts the input voltage by a process ...
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... A/D converter if set to “1”. Writing a “0” to this bit will put the ADC in power down mode (idle mode). Bit 3-0 = D3-D0. Not used A/D Converter Data Register (ADR) Address: 0D0h — D7 Bit 7-0 = D7- Bit A/D Conversion Result. ST62T45B/E45B Read/Write 7 EOC STA PDS D3 D2 Read only ...
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... ST62T45B/E45B 4.4 SERIAL PERIPHERAL INTERFACE (SPI) The on-chip SPI is an optimized serial synchro- nous interface that supports a wide range of in- dustry standard SPI specifications. The on-chip SPI is controlled by small and simple user soft- ware to perform serial data exchange. The serial shift clock can be implemented either by software ...
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... SCL clock frequency by simply putting the SCL I/O line in output open-drain mode and writ- ing a zero into the corresponding data register bit. ST62T45B/E45B possible to directly read the Sin pin directly through the port register, the software can detect a difference between internal data and external data (master mode) ...
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... ST62T45B/E45B 4.5 LCD CONTROLLER-DRIVER On-chip LCD driver includes all features required for LCD driving, including multiplexing of the com- mon plates. Multiplexing allows to increase dis- play capability without increasing the number of segment outputs. In that case, the display capabil- ity is equal to the product of the number of com- mon plates with the number of segment outputs ...
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... Reserved Note: For display voltages V tivity of the divider may be too high for some appli- cations (especially using 1/3 or 1/4 duty display mode). In that case an external resistive divider must be used to achieve the desired resistivity. ST62T45B/E45B LCDOFF V LCD LCD2 ...
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... ST62T45B/E45B LCD CONTROLLER-DRIVER (Continued) Figure 29. Typical Network to connect to V pins if VLCD 4.5V V LCD V LCD2/3 www.DataSheet4U.com V LCD1 Figure 30. Addressing Map of the LCD RAM RAM Address 50/72 49 Typical External resistances values are in the LCD range of 100 k to 150 k ...
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... LF0, LF1, LF2 define the 32kHz division factor as shown in Table 21 Table 21. 32kHz Division Factor for Base Frequency Selection Division Factor LF2 LF1 INT ST62T45B/E45B DS0 HF2 HF1 HF0 LF2 LF1 LF0 32kHz Division Factor 0 0 512 0 1 386 1 ...
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... ST62T45B/E45B 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction ...
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... Addressing Mode Bytes Short Direct 1 Short Direct 1 Short Direct 1 Short Direct 1 Short Direct 1 Short Direct 1 Short Direct 1 Short Direct 1 Direct 2 Direct 2 Indirect 1 Indirect 1 Indirect 1 Indirect 1 Immediate 2 Immediate 3 ST62T45B/E45B Flags Cycles ...
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... ST62T45B/E45B INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space memory con- Table 23. Arithmetic & Logic Instructions Instruction www ...
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... Addressing Mode Bytes Bit Direct 2 Bit Direct 2 Addressing Mode Bytes Inherent 1 Inherent 1 Inherent 1 Inherent 1 Inherent 1 Addressing Mode Bytes Extended 2 Extended 2 ST62T45B/E45B Flags Cycles rr. Data space register . Affected. The tested bit is shifted into carry Not Affected Flags Cycles Z ...
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... ST62T45B/E45B Opcode Map Summary.The following table contains an opcode map for the instructions used by the ST6 LOW 0 0000 HI 2 JRNZ 0000 1 pcr 2 2 JRNZ 0001 1 pcr 2 2 JRNZ www.DataSheet4U.com 0010 1 pcr 2 2 JRNZ 0011 1 pcr 2 2 JRNZ ...
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... Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement ST62T45B/E45B LOW 1101 1110 1111 JRZ 4 LDI 2 JRC 4 LD rr,nn e a,(y) pcr 3 imm 1 prc 1 ind JRZ 4 ...
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... ST62T45B/E45B 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V www ...
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... The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. Test Condition s 6 Suffix Version 1 Suffix Version f = 4MHz OSC fosc= 8MHz 4. 4 4 recommanded. 3 3.5 4 4.5 SUPPLY VOLTAGE ( ST62T45B/E45B Value Unit Min. Typ. Max. - 3.0 6.0 4.5 6.0 0 4.0 MHz ...
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... ST62T45B/E45B 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins Hysteresis Voltage V Hys www.DataSheet4U.com All Input pins Low Level Output Voltage All Output pins V OL Low Level Output Voltage ...
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... Test Condi tions f > 1.2MHz (1) (2) OSC f > 32kHz OSC f = 8MHz OSC Conversion result when Conversion result when 4.5V DD ST62T45B/E45B Value Unit Min. Typ. Max. 100 ms 100 ns 100 300,000 1 million cycles 10 years Value Unit Min ...
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... ST62T45B/E45B 6.6 TIMER CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol f Input Frequency on TIMER Pin Pulse Width at TIMER Pin* W www.DataSheet4U.com Note*: When available. 6.7 SPI CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol 6.8 LCD ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) ...
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... A1 0.50 B 0.35 0.40 0.50 0.014 0.016 0.020 C 0.13 0.15 0.23 0.005 0.006 0.009 D 16.65 17.20 17.75 0.656 0.677 0.699 D1 13.57 13.97 14.37 D2 13.06 13.46 13.86 0.514 0.530 0.546 D3 12.00 e 1.00 G 12.70 G2 0.96 L 0.35 0.80 Ø 8.31 CQFP052W N ST62T45B/E45B inches Min Typ Max 3.40 0.134 0.010 0.50 0.014 0.020 0.23 0.005 0.009 0.472 0.472 0.039 0.063 Number of Pins 52 inches Min Typ Max 3.27 0.129 ...
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... ST62T45B/E45B GENERAL INFORMATION (Continued) 7.2 PACKAGE THERMAL CHARACTERISTIC Symbol RthJA Thermal Resistance 7.3 ORDERING INFORMATION www.DataSheet4U.com Table 28. OTP/EPROM VERSION ORDERING INFORMATION Sales Type ST62E45BG1 ST62T45BQ6 64/72 63 Parameter Test Conditions PQFP52 CQFP52W Program I/O Memory (Bytes) 3884 (EPROM 3884 (OTP) Value Unit Min. Typ. Max. ...
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R 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency www.DataSheet4U.com -40 to +85 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User ...
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... ST62P45B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62P45B is the Factory Advanced Service T echnique ROM ST62T45B OTP devices. It offers the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version. www.DataSheet4U.com 1.2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON ...
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Customer Address Contact www.DataSheet4U.com Phone No Reference SGS-THOMSON Microelectronics references Device: Package: Temperature Range: Watchdog Selection: NMI Pull-Up Selection: TIMER Pull-Up Selection: Readout Protection: Comments : Number of segments and backplanes used: Supply Operating Range in the application: Oscillator Fequency ...
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ST62P45B Notes: www.DataSheet4U.com 68/72 67 ...
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R 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency www.DataSheet4U.com -40 to +85 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User ...
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... ST6245B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6245B is mask programmed ROM version of ST62T45B OTP devices. It offers the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form www.DataSheet4U.com TES T 100 ...
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Customer Address Contact Phone No www.DataSheet4U.com Reference SGS-THOMSON Microelectronics references Device: Package: Temperature Range: Special Marking: Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. Maximum character count: Watchdog Selection: NMI Pull-Up Selection: TIMER Pull-Up Selection: ROM Readout ...
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ST6245B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options. ...