D63GS NEC, D63GS Datasheet - Page 24

• Manufacturer Part Number: D63GS
• Description: Search -----> UPD63GS
• Manufacturer: NEC

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5.3 Standby Mode Release Timing
24
0/1
b
Notes 1. When setting HALT # 110B, configure a key matrix by using the K
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
(1) STOP Mode Release Timing
Caution When a release condition is established in the STOP mode, the device is released from the STOP
0
1
3
Operand Value of
HALT Instruction
Any of the
combinations of
b
2
b
0
0
1
1
b
2. At least one of the S
2
1
b
mode, and goes into a wait state. At this time, if the release condition is not held, the device
goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP
mode, it is necessary to hold the release condition longer than the wait time.
0
internal reset takes effect at the time of program hang-up.
(The internal reset does not take effect even when both pins are in OUTPUT mode.)
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
3. Write the NOP instruction as the first instruction after STOP mode is released.
above
Table 5-3. Standby Mode Setup (HALT #b
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output permit flag are cleared to 0.
b
0
1
1
0
1
Standby
release signal
b
Clock
0
1
0
1
Figure 5-1. STOP Mode Cancelation by Release Condition
0
Setting Mode
STOP
STOP
STOP
STOP
HALT
0
and S
Note 1
OPERATING
Oscillation
mode
HALT instruction
1
(STOP mode)
pins (the pin used for releasing the standby) must be in INPUT mode.
All K
All K
The K
I/O
I/O
I/O0
Precondition for Setup
STOP mode
[The following condition is added in addition to the above.]
pins are high-level output.
pins are high-level output.
Oscillation
stopped
pin is high-level output.
—
—
3
b
2
b
1
b
0
HALT mode
B) and Release Conditions
(52/f
Wait
X
+ )
Oscillation
: Oscillation growth time
High level is input to at least one
of K
High level is input to at least one
of K
High level is input to at least one
of K
High level is input to at least one
of S
When the timer’s down counter is 0
I/O0
OPERATING
I
I
I
0
pins.
pins.
pins.
pin and the K
and S
mode
Release Condition
1
pins
Note 2
PD63, 63A, 64
I
pin so that an
.