D63GS NEC, D63GS Datasheet - Page 26

• Manufacturer Part Number: D63GS
• Description: Search -----> UPD63GS
• Manufacturer: NEC

www.DataSheet4U.com
6. RESET PIN
are fixed to the GND.
246 to 694 of the system clock (f
26
PC (10 bits)
SP (1 bit)
Data
memory
Accumulator (A)
Status flag (F)
Carry flag (CY)
Timer (10 bits)
Port register
Control register P3
The system reset takes effect by inputting low level to the RESET pin.
While the RESET pin is at low level, the system clock oscillation circuit is stopped and the X
If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting
The RESET pin outputs low level when the POC circuit (mask option) is in operation.
Caution When connecting a reset IC to the RESET pin, ensure that the IC is of the N-ch open drain output
Notes 1. The following resets are available.
Hardware
2. Refers to the value by the K
R1-RF
R0 = DP
type.
• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
• Reset when executing the RLZ instruction (when A = 0)
• Reset by stack pointer’s overflow or underflow
In order to prevent malfunction, be sure to input a low level to more than one of pins K
reset is released (when RESET pin changes from low level to high level, or POC is released due to
supply voltage startup).
the precondition)
P0
P1
P4
RESET
• RESET Input in Operation
• Resetting by Internal POC Circuit in Operation
• Resetting by Other Factors
000H
0B
000H
Undefined
Undefined
0B
0B
000H
FFH
03H
26H
FH
Note 2
Figure 6-1. Reset Operation by RESET Input
X
Table 6-1. Hardware Statuses After Reset
OPERATING mode or
STANDBY mode
).
I
pin status.
Note 1
Oscillation
stopped
(246 to 694)/f
HALT mode
• RESET Input During STANDBY Mode
• Resetting by the Internal POC Circuit During
Previous status retained
STANDBY Mode
Wait
: Oscillation growth time
X
+
OPERATING
0 address start
mode
PD63, 63A, 64
IN
and X
I0
to K
OUT
I3
when
pins