LTC2412 Linear Technology, LTC2412 Datasheet - Page 17

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS = LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F
SERIAL INTERFACE TIMING MODES
The LTC2412’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and autostart. The
Table 4. LTC2412 Interface Timing Modes
Configuration
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
(EXTERNAL)
SDO
SCK
CS
CONVERSION
Hi-Z
TEST EOC
U
SLEEP
(OPTIONAL)
TEST EOC
U
SLEEP
Hi-Z
Figure 5. External Serial Clock, Single Cycle Operation
W
BIT 31
EOC
ANALOG INPUT RANGE
CH0/CH1
–0.5V
BIT 30
O
.
REF
External
External
Internal
Internal
Source
U
TO 0.5V
0.1V TO V
REFERENCE
SCK
BIT 29
VOLTAGE
SIG
1 F
2.7V TO 5.5V
REF
CC
BIT 28
MSB
1
2
3
4
5
6
7
V
REF
REF
CH0
CH0
CH1
CH1
CC
LTC2412
+
–
+
–
+
–
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (F
an external oscillator connected to the F
Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
BIT 27
DATA OUTPUT
GND
SDO
Conversion
CS and SCK
SCK
Continuous
CS
F
O
Control
Cycle
CS
SCK
14
13
12
11
8, 9, 10, 15, 16
BIT 26
3-WIRE
SPI INTERFACE
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
CS and SCK
BIT 5
LSB
Control
Internal
Output
CS
Data
SCK
O
= LOW or F
SUB LSB
BIT 0
LTC2412
O
Connection
Waveforms
Figures 5, 6
Figures 8, 9
Figure 10
pin. Refer to
Figure 7
O
and
CONVERSION
= HIGH) or
Hi-Z
17
TEST EOC
2412 F05
2412f