LTC2412 Linear Technology, LTC2412 Datasheet - Page 18

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2412
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. On the
32nd falling edge of SCK, the device begins a new conver-
sion. SDO goes HIGH (EOC = 1) indicating a conversion is
in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
18
(EXTERNAL)
SDO
SCK
SLEEP
CS
OUTPUT
DATA
BIT 0
EOC
U
CONVERSION
Hi-Z
TEST EOC
U
Hi-Z
Figure 6. External Serial Clock, Reduced Data Output Length
TEST EOC (OPTIONAL)
SLEEP
W
ANALOG INPUT RANGE
SLEEP
–0.5V
Hi-Z
REF
TO 0.5V
U
0.1V TO V
REFERENCE
BIT 31
EOC
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
CH0/CH1
BIT 30
1
2
3
4
5
6
7
V
REF
REF
CH0
CH0
CH1
CH1
CC
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 32 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
LTC2412
+
–
+
–
+
–
BIT 29
SDO
GND
SCK
SIG
CS
F
O
14
13
12
11
8, 9, 10, 15, 16
DATA OUTPUT
BIT 28
MSB
3-WIRE
SPI INTERFACE
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 27
BIT 9
BIT 8
CONVERSION
Hi-Z
TEST EOC
2412 F06
2412f